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Searched refs:fpu_spill_mask_ (Results 1 – 5 of 5) sorted by relevance

/art/compiler/optimizing/
Dcode_generator.h230 uint32_t GetFpuSpillMask() const { return fpu_spill_mask_; } in GetFpuSpillMask()
239 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()
603 fpu_spill_mask_(0), in CodeGenerator()
643 return POPCOUNT(fpu_spill_mask_) * GetFloatingPointSpillSlotSize(); in GetFpuSpillSize()
697 uint32_t fpu_spill_mask_; variable
Dcode_generator_arm_vixl.cc2120 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()
2125 if (fpu_spill_mask_ != 0) { in ComputeSpillMask()
2126 uint32_t least_significant_bit = LeastSignificantBit(fpu_spill_mask_); in ComputeSpillMask()
2127 uint32_t most_significant_bit = MostSignificantBit(fpu_spill_mask_); in ComputeSpillMask()
2129 fpu_spill_mask_ |= (1 << i); in ComputeSpillMask()
2162 if (fpu_spill_mask_ != 0) { in GenerateFrameEntry()
2163 uint32_t first = LeastSignificantBit(fpu_spill_mask_); in GenerateFrameEntry()
2166 DCHECK_EQ(fpu_spill_mask_ >> CTZ(fpu_spill_mask_), ~0u >> (32 - POPCOUNT(fpu_spill_mask_))); in GenerateFrameEntry()
2168 __ Vpush(SRegisterList(vixl32::SRegister(first), POPCOUNT(fpu_spill_mask_))); in GenerateFrameEntry()
2169 GetAssembler()->cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(fpu_spill_mask_)); in GenerateFrameEntry()
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Dcode_generator_arm.cc2040 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()
2045 if (fpu_spill_mask_ != 0) { in ComputeSpillMask()
2046 uint32_t least_significant_bit = LeastSignificantBit(fpu_spill_mask_); in ComputeSpillMask()
2047 uint32_t most_significant_bit = MostSignificantBit(fpu_spill_mask_); in ComputeSpillMask()
2049 fpu_spill_mask_ |= (1 << i); in ComputeSpillMask()
2081 if (fpu_spill_mask_ != 0) { in GenerateFrameEntry()
2082 SRegister start_register = SRegister(LeastSignificantBit(fpu_spill_mask_)); in GenerateFrameEntry()
2083 __ vpushs(start_register, POPCOUNT(fpu_spill_mask_)); in GenerateFrameEntry()
2084 __ cfi().AdjustCFAOffset(kArmWordSize * POPCOUNT(fpu_spill_mask_)); in GenerateFrameEntry()
2085 __ cfi().RelOffsetForMany(DWARFReg(S0), 0, fpu_spill_mask_, kArmWordSize); in GenerateFrameEntry()
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Dcode_generator_mips.cc1236 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()
1241 if ((fpu_spill_mask_ != 0) && (POPCOUNT(core_spill_mask_) % 2 != 0)) { in ComputeSpillMask()
1274 CHECK_EQ(fpu_spill_mask_, 0u); in GenerateFrameEntry()
1301 for (uint32_t mask = fpu_spill_mask_; mask != 0; ) { in GenerateFrameEntry()
1341 for (uint32_t mask = fpu_spill_mask_; mask != 0; ) { in GenerateFrameExit()
Dcode_generator_arm64.cc1603 DCHECK(ArtVixlRegCodeCoherentForRegSet(0, 0, fpu_spill_mask_, in GetFramePreservedFPRegisters()
1606 fpu_spill_mask_); in GetFramePreservedFPRegisters()