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Searched refs:imm16 (Results 1 – 7 of 7) sorted by relevance

/art/compiler/utils/mips/
Dassembler_mips.h213 void Addiu(Register rt, Register rs, uint16_t imm16);
234 void Andi(Register rt, Register rs, uint16_t imm16);
236 void Ori(Register rt, Register rs, uint16_t imm16);
238 void Xori(Register rt, Register rs, uint16_t imm16);
268 void Lb(Register rt, Register rs, uint16_t imm16);
269 void Lh(Register rt, Register rs, uint16_t imm16);
270 void Lw(Register rt, Register rs, uint16_t imm16);
271 void Lwl(Register rt, Register rs, uint16_t imm16);
272 void Lwr(Register rt, Register rs, uint16_t imm16);
273 void Lbu(Register rt, Register rs, uint16_t imm16);
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Dassembler_mips.cc411 void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) { in Addiu() argument
412 DsFsmInstrRrr(EmitI(0x9, rs, rt, imm16), rt, rs, rs); in Addiu()
507 void MipsAssembler::Andi(Register rt, Register rs, uint16_t imm16) { in Andi() argument
508 DsFsmInstrRrr(EmitI(0xc, rs, rt, imm16), rt, rs, rs); in Andi()
515 void MipsAssembler::Ori(Register rt, Register rs, uint16_t imm16) { in Ori() argument
516 DsFsmInstrRrr(EmitI(0xd, rs, rt, imm16), rt, rs, rs); in Ori()
523 void MipsAssembler::Xori(Register rt, Register rs, uint16_t imm16) { in Xori() argument
524 DsFsmInstrRrr(EmitI(0xe, rs, rt, imm16), rt, rs, rs); in Xori()
664 void MipsAssembler::Lb(Register rt, Register rs, uint16_t imm16) { in Lb() argument
665 DsFsmInstrRrr(EmitI(0x20, rs, rt, imm16), rt, rs, rs); in Lb()
[all …]
/art/compiler/utils/mips64/
Dassembler_mips64.cc307 void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Addiu() argument
308 EmitI(0x9, rs, rt, imm16); in Addiu()
315 void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Daddiu() argument
316 EmitI(0x19, rs, rt, imm16); in Daddiu()
379 void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Andi() argument
380 EmitI(0xc, rs, rt, imm16); in Andi()
387 void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Ori() argument
388 EmitI(0xd, rs, rt, imm16); in Ori()
395 void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { in Xori() argument
396 EmitI(0xe, rs, rt, imm16); in Xori()
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Dassembler_mips64.h443 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
445 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
463 void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
465 void Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
467 void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
507 void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
508 void Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
509 void Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16);
510 void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
511 void Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
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/art/compiler/utils/arm/
Dassembler_thumb2.cc2651 void Thumb2Assembler::movw(Register rd, uint16_t imm16, Condition cond) { in movw() argument
2654 uint32_t imm4 = (imm16 >> 12) & 15U /* 0b1111 */; in movw()
2655 uint32_t i = (imm16 >> 11) & 1U /* 0b1 */; in movw()
2656 uint32_t imm3 = (imm16 >> 8) & 7U /* 0b111 */; in movw()
2657 uint32_t imm8 = imm16 & 0xff; in movw()
2669 void Thumb2Assembler::movt(Register rd, uint16_t imm16, Condition cond) { in movt() argument
2672 uint32_t imm4 = (imm16 >> 12) & 15U /* 0b1111 */; in movt()
2673 uint32_t i = (imm16 >> 11) & 1U /* 0b1 */; in movt()
2674 uint32_t imm3 = (imm16 >> 8) & 7U /* 0b111 */; in movt()
2675 uint32_t imm8 = imm16 & 0xff; in movt()
Dassembler_arm.h512 virtual void movw(Register rd, uint16_t imm16, Condition cond = AL) = 0;
513 virtual void movt(Register rd, uint16_t imm16, Condition cond = AL) = 0;
570 virtual void bkpt(uint16_t imm16) = 0;
Dassembler_thumb2.h121 void movw(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
122 void movt(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
188 void bkpt(uint16_t imm16) OVERRIDE;