Searched refs:r6 (Results 1 – 11 of 11) sorted by relevance
/art/runtime/arch/mips/ |
D | instruction_set_features_mips.cc | 50 static void GetFlagsFromCppDefined(bool* mips_isa_gte2, bool* r6, bool* fpu_32bit) { in GetFlagsFromCppDefined() argument 65 *r6 = true; in GetFlagsFromCppDefined() 67 *r6 = false; in GetFlagsFromCppDefined() 78 bool r6; in FromVariant() local 79 GetFlagsFromCppDefined(&mips_isa_gte2, &r6, &fpu_32bit); in FromVariant() 87 r6 = (variant[kPrefixLength] >= '6'); in FromVariant() 103 return MipsFeaturesUniquePtr(new MipsInstructionSetFeatures(fpu_32bit, mips_isa_gte2, r6)); in FromVariant() 109 bool r6 = (bitmap & kR6) != 0; in FromBitmap() local 110 return MipsFeaturesUniquePtr(new MipsInstructionSetFeatures(fpu_32bit, mips_isa_gte2, r6)); in FromBitmap() 116 bool r6; in FromCppDefines() local [all …]
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D | instruction_set_features_mips.h | 87 MipsInstructionSetFeatures(bool fpu_32bit, bool mips_isa_gte2, bool r6) in MipsInstructionSetFeatures() argument 91 r6_(r6) { in MipsInstructionSetFeatures() 93 if (r6) { in MipsInstructionSetFeatures()
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/art/compiler/optimizing/ |
D | optimizing_cfi_test_expected.inc | 11 // 0x00000000: push {r5, r6, lr} 14 // 0x00000002: .cfi_offset: r6 at cfa-8 29 // 0x0000000e: pop {r5, r6, pc} 79 // 0x00000001: .cfi_offset: r6 at cfa-8 93 // 0x0000000b: .cfi_restore: r6 112 // 0x00000001: .cfi_offset: r6 at cfa-16 134 // 0x00000028: .cfi_restore: r6 250 // 0x00000000: push {r5, r6, lr} 253 // 0x00000002: .cfi_offset: r6 at cfa-8 335 // 0x00000094: pop {r5, r6, pc} [all …]
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D | code_generator_arm_vixl.h | 86 vixl::aarch32::r6,
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/art/runtime/interpreter/mterp/arm/ |
D | entry.S | 40 .cfi_rel_offset r6, 12
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D | header.S | 96 #define rSELF r6
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/art/compiler/jni/ |
D | jni_cfi_test_expected.inc | 19 // 0x00000000: push {r5, r6, r7, r8, r10, r11, lr} 22 // 0x00000004: .cfi_offset: r6 at cfa-24 78 // 0x00000020: pop {r5, r6, r7, r8, r10, r11, pc} 201 // 0x00000002: .cfi_offset: r6 at cfa-12 225 // 0x00000024: .cfi_restore: r6 270 // 0x00000009: .cfi_offset: r6 at cfa-48 309 // 0x00000076: .cfi_restore: r6 365 // 0x00000030: sw r6, +76(r29)
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/art/runtime/arch/arm/ |
D | quick_entrypoints_arm.S | 34 .cfi_rel_offset r6, 8 73 .cfi_rel_offset r6, 4 98 .cfi_restore r6 123 .cfi_rel_offset r6, 16 164 .cfi_restore r6 209 .cfi_rel_offset r6, 24 231 .cfi_restore r6 2015 CONDITIONAL_CBZ \reg, r6, \dest 2142 READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg06, r6
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/art/compiler/utils/arm/ |
D | assembler_arm_vixl.cc | 243 tmp_reg = (base.GetCode() != 5) ? r5 : r6; in StoreToOffset() 273 CHECK(tmp_reg.Is(r5) || tmp_reg.Is(r6)) << tmp_reg; in StoreToOffset()
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/art/runtime/interpreter/mterp/out/ |
D | mterp_arm.S | 103 #define rSELF r6 359 .cfi_rel_offset r6, 12
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/art/compiler/utils/ |
D | assembler_thumb_test_expected.cc.inc | 5461 " 0: e92d 4de0 stmdb sp!, {r5, r6, r7, r8, sl, fp, lr}\n", 5611 " 218: e8bd 8de0 ldmia.w sp!, {r5, r6, r7, r8, sl, fp, pc}\n",
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