Searched refs:reg_s (Results 1 – 3 of 3) sorted by relevance
705 EXPECT_TRUE(vixl::aarch64::s0.Is(Arm64Assembler::reg_s(S0))); in TEST()706 EXPECT_TRUE(vixl::aarch64::s1.Is(Arm64Assembler::reg_s(S1))); in TEST()707 EXPECT_TRUE(vixl::aarch64::s2.Is(Arm64Assembler::reg_s(S2))); in TEST()708 EXPECT_TRUE(vixl::aarch64::s3.Is(Arm64Assembler::reg_s(S3))); in TEST()709 EXPECT_TRUE(vixl::aarch64::s4.Is(Arm64Assembler::reg_s(S4))); in TEST()710 EXPECT_TRUE(vixl::aarch64::s5.Is(Arm64Assembler::reg_s(S5))); in TEST()711 EXPECT_TRUE(vixl::aarch64::s6.Is(Arm64Assembler::reg_s(S6))); in TEST()712 EXPECT_TRUE(vixl::aarch64::s7.Is(Arm64Assembler::reg_s(S7))); in TEST()713 EXPECT_TRUE(vixl::aarch64::s8.Is(Arm64Assembler::reg_s(S8))); in TEST()714 EXPECT_TRUE(vixl::aarch64::s9.Is(Arm64Assembler::reg_s(S9))); in TEST()[all …]
39 #define reg_s(S) Arm64Assembler::reg_s(S) macro120 ___ Str(reg_s(source), MEM_OP(reg_x(base), offset)); in StoreSToOffset()247 ___ Ldr(reg_s(dest), MEM_OP(reg_x(base), offset)); in LoadSFromOffset()275 ___ Ldr(reg_s(dest.AsSRegister()), MEM_OP(reg_x(base), offset)); in Load()352 ___ Fmov(reg_s(dst.AsSRegister()), reg_s(src.AsSRegister())); in Move()
132 static vixl::aarch64::FPRegister reg_s(int code) { in reg_s() function