| /art/runtime/arch/arm/ |
| D | jni_entrypoints_arm.S | 24 push {r0, r1, r2, r3, lr} @ spill regs
38 pop {r0, r1, r2, r3, lr} @ restore regs
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.cc | 363 void ArmVIXLAssembler::StoreRegisterList(RegList regs, size_t stack_offset) { in StoreRegisterList() argument
364 int number_of_regs = POPCOUNT(static_cast<uint32_t>(regs)); in StoreRegisterList()
371 DCHECK_EQ(regs & (1u << base.GetCode()), 0u); in StoreRegisterList()
374 ___ Stm(base, NO_WRITE_BACK, RegisterList(regs)); in StoreRegisterList()
376 for (uint32_t i : LowToHighBits(static_cast<uint32_t>(regs))) { in StoreRegisterList()
384 void ArmVIXLAssembler::LoadRegisterList(RegList regs, size_t stack_offset) { in LoadRegisterList() argument
385 int number_of_regs = POPCOUNT(static_cast<uint32_t>(regs)); in LoadRegisterList()
394 ___ Ldm(base, NO_WRITE_BACK, RegisterList(regs)); in LoadRegisterList()
396 for (uint32_t i : LowToHighBits(static_cast<uint32_t>(regs))) { in LoadRegisterList()
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| /art/runtime/arch/arm64/ |
| D | fault_handler_arm64.cc | 58 *out_method = reinterpret_cast<ArtMethod*>(sc->regs[0]); in GetMethodAndReturnPcAndSp()
86 sc->regs[30] = reinterpret_cast<uintptr_t>(info->si_addr); in Action()
142 sc->regs[30] = sc->pc + 4; in Action()
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| /art/runtime/interpreter/mterp/arm/ |
| D | op_move_result_wide.S | 6 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
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| D | op_const_wide_16.S | 6 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
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| D | op_const_wide_high16.S | 7 CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs
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| D | funopWider.S | 14 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs
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| D | op_move_wide_16.S | 9 CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs
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| D | op_move_wide.S | 8 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
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| D | op_move_wide_from16.S | 8 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
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| D | fbinopWide2addr.S | 13 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs
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| D | unopWider.S | 15 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
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| D | op_const_wide_32.S | 7 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
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| D | unopWide.S | 15 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
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| D | fbinopWide.S | 19 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs
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| D | op_sget_wide.S | 19 CLEAR_SHADOW_PAIR r9, r2, ip @ Zero out the shadow regs
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| D | op_iget_wide.S | 18 CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs
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| D | op_const_wide.S | 9 CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs
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| D | binopWide2addr.S | 27 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
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| D | footer.S | 284 ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return
295 ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return
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| D | binopWide.S | 31 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs
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| D | op_ushr_long_2addr.S | 9 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
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| D | op_aget_wide.S | 13 CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs
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| D | op_shl_long_2addr.S | 9 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
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| D | op_shr_long_2addr.S | 9 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
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