Searched refs:rlo (Results 1 – 8 of 8) sorted by relevance
| /art/runtime/interpreter/mterp/mips/ |
| D | header.S | 365 #define SET_VREG64(rlo, rhi, rix) \ argument
367 sw rlo, 0(t8); \
373 #define SET_VREG64(rlo, rhi, rix) \ argument
377 sw rlo, 0(t8); \
403 #define SET_VREG64_F(rlo, rhi, rix) \ argument
406 mfhc1 AT, rlo; \
407 s.s rlo, 0(t8); \
414 #define SET_VREG64_F(rlo, rhi, rix) \ argument
421 mfhc1 AT, rlo; \
424 s.s rlo, 0(t8)
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| D | op_shr_long_2addr.S | 17 srl v0, a0, a2 # rlo<- alo >> (shift&31)
21 or v0, a1 # rlo<- rlo | ahi
27 SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi
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| D | op_ushr_long_2addr.S | 18 srl v0, a0, a2 # rlo<- alo >> (shift&31)
22 or v0, a1 # rlo<- rlo | ahi
27 SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi
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| D | op_ushr_long.S | 22 srl v0, a0, a2 # rlo<- alo >> (shift&31)
26 or v0, a1 # rlo<- rlo | ahi
31 SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi
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| D | op_shr_long.S | 21 srl v0, a0, a2 # rlo<- alo >> (shift&31)
25 or v0, a1 # rlo<- rlo | ahi
31 SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi
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| D | op_shl_long_2addr.S | 16 sll v0, a0, a2 # rlo<- alo << (shift&31)
27 SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi
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| D | op_shl_long.S | 20 sll v0, a0, a2 # rlo<- alo << (shift&31)
31 SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi
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| /art/runtime/interpreter/mterp/out/ |
| D | mterp_mips.S | 372 #define SET_VREG64(rlo, rhi, rix) \ argument
374 sw rlo, 0(t8); \
380 #define SET_VREG64(rlo, rhi, rix) \ argument
384 sw rlo, 0(t8); \
410 #define SET_VREG64_F(rlo, rhi, rix) \ argument
413 mfhc1 AT, rlo; \
414 s.s rlo, 0(t8); \
421 #define SET_VREG64_F(rlo, rhi, rix) \ argument
428 mfhc1 AT, rlo; \
431 s.s rlo, 0(t8)
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