| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 332 Register rs, in EmitR() argument
337 CHECK_NE(rs, kNoRegister); in EmitR()
341 static_cast<uint32_t>(rs) << kRsShift | in EmitR()
350 uint32_t MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { in EmitI() argument
351 CHECK_NE(rs, kNoRegister); in EmitI()
354 static_cast<uint32_t>(rs) << kRsShift | in EmitI()
361 uint32_t MipsAssembler::EmitI21(int opcode, Register rs, uint32_t imm21) { in EmitI21() argument
362 CHECK_NE(rs, kNoRegister); in EmitI21()
365 static_cast<uint32_t>(rs) << kRsShift | in EmitI21()
407 void MipsAssembler::Addu(Register rd, Register rs, Register rt) { in Addu() argument
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| D | assembler_mips.h | 212 void Addu(Register rd, Register rs, Register rt);
213 void Addiu(Register rt, Register rs, uint16_t imm16);
214 void Subu(Register rd, Register rs, Register rt);
216 void MultR2(Register rs, Register rt); // R2
217 void MultuR2(Register rs, Register rt); // R2
218 void DivR2(Register rs, Register rt); // R2
219 void DivuR2(Register rs, Register rt); // R2
220 void MulR2(Register rd, Register rs, Register rt); // R2
221 void DivR2(Register rd, Register rs, Register rt); // R2
222 void ModR2(Register rd, Register rs, Register rt); // R2
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 99 void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, in EmitR() argument
101 CHECK_NE(rs, kNoGpuRegister); in EmitR()
105 static_cast<uint32_t>(rs) << kRsShift | in EmitR()
113 void Mips64Assembler::EmitRsd(int opcode, GpuRegister rs, GpuRegister rd, in EmitRsd() argument
115 CHECK_NE(rs, kNoGpuRegister); in EmitRsd()
118 static_cast<uint32_t>(rs) << kRsShift | in EmitRsd()
139 void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { in EmitI() argument
140 CHECK_NE(rs, kNoGpuRegister); in EmitI()
143 static_cast<uint32_t>(rs) << kRsShift | in EmitI()
149 void Mips64Assembler::EmitI21(int opcode, GpuRegister rs, uint32_t imm21) { in EmitI21() argument
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| D | assembler_mips64.h | 442 void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
443 void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
444 void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
445 void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
446 void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
447 void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
449 void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
450 void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
451 void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
452 void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
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| D | assembler_mips64_test.cc | 2410 void Addiu(mips64::GpuRegister rd, mips64::GpuRegister rs, uint16_t c) { in Addiu()
2411 regs_[rd] = static_cast<int32_t>(regs_[rs] + SignExtend16To64(c)); in Addiu()
2413 void Daddiu(mips64::GpuRegister rd, mips64::GpuRegister rs, uint16_t c) { in Daddiu()
2414 regs_[rd] = regs_[rs] + SignExtend16To64(c); in Daddiu()
2422 void Dinsu(mips64::GpuRegister rt, mips64::GpuRegister rs, int pos, int size) { in Dinsu()
2429 regs_[rt] = (regs_[rt] & dsk_mask) | ((regs_[rs] & src_mask) << pos); in Dinsu()
2446 void Ori(mips64::GpuRegister rd, mips64::GpuRegister rs, uint16_t c) { in Ori()
2447 regs_[rd] = regs_[rs] | c; in Ori()
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| /art/disassembler/ |
| D | disassembler_mips.cc | 464 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type. in Dump() local
544 args << StringPrintf("%+d(r%d)", offset, rs); in Dump()
550 args << StringPrintf("%+d(r%d)", offset, rs); in Dump()
551 if (rs == 17) { in Dump()
586 args << offset << " ; move r" << rs << ", "; in Dump()
590 case 'S': args << 'r' << rs; break; in Dump()
591 case 's': args << 'f' << rs; break; in Dump()
731 if (((op == 0x36 || op == 0x3E) && rs == 0 && rt != 0) && // ji[al]c in Dump()
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| /art/runtime/interpreter/mterp/mips/ |
| D | header.S | 187 #define LSA(rd, rs, rt, sa) \ argument
189 lsa rd, rs, rt, sa; \
191 addu rd, rs, rt; \
196 #define LSA(rd, rs, rt, sa) \ argument
200 sll AT, rs, sa; \
204 addu rd, rs, rt; \
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| /art/compiler/utils/arm/ |
| D | assembler_arm.h | 148 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), in ShifterOperand() argument
149 rs_(rs), in ShifterOperand()
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| D | assembler_thumb2.h | 756 Register rs);
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| /art/runtime/interpreter/mterp/out/ |
| D | mterp_mips.S | 194 #define LSA(rd, rs, rt, sa) \ argument
196 lsa rd, rs, rt, sa; \
198 addu rd, rs, rt; \
203 #define LSA(rd, rs, rt, sa) \ argument
207 sll AT, rs, sa; \
211 addu rd, rs, rt; \
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