| /art/compiler/utils/mips64/ |
| D | assembler_mips64.cc | 100 int shamt, int funct) { in EmitR() argument
108 shamt << kShamtShift | in EmitR()
114 int shamt, int funct) { in EmitRsd() argument
121 shamt << kShamtShift | in EmitRsd()
127 int shamt, int funct) { in EmitRtd() argument
134 shamt << kShamtShift | in EmitRtd()
476 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) { in Sll() argument
477 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00); in Sll()
480 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) { in Srl() argument
481 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02); in Srl()
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| D | assembler_mips64.h | 486 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
487 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
488 void Rotr(GpuRegister rd, GpuRegister rt, int shamt);
489 void Sra(GpuRegister rd, GpuRegister rt, int shamt);
494 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
495 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
496 void Drotr(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
497 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
498 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
499 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
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| D | assembler_mips64_test.cc | 2431 void Dsll(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsll()
2432 regs_[rd] = regs_[rt] << (shamt & 0x1f); in Dsll()
2434 void Dsll32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsll32()
2435 regs_[rd] = regs_[rt] << (32 + (shamt & 0x1f)); in Dsll32()
2437 void Dsrl(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsrl()
2438 regs_[rd] = regs_[rt] >> (shamt & 0x1f); in Dsrl()
2440 void Dsrl32(mips64::GpuRegister rd, mips64::GpuRegister rt, int shamt) { in Dsrl32()
2441 regs_[rd] = regs_[rt] >> (32 + (shamt & 0x1f)); in Dsrl32()
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| /art/compiler/utils/mips/ |
| D | assembler_mips.cc | 335 int shamt, in EmitR() argument
344 shamt << kShamtShift | in EmitR()
588 void MipsAssembler::Sll(Register rd, Register rt, int shamt) { in Sll() argument
589 CHECK(IsUint<5>(shamt)) << shamt; in Sll()
590 DsFsmInstrRrr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x00), rd, rt, rt); in Sll()
593 void MipsAssembler::Srl(Register rd, Register rt, int shamt) { in Srl() argument
594 CHECK(IsUint<5>(shamt)) << shamt; in Srl()
595 DsFsmInstrRrr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x02), rd, rt, rt); in Srl()
598 void MipsAssembler::Rotr(Register rd, Register rt, int shamt) { in Rotr() argument
599 CHECK(IsUint<5>(shamt)) << shamt; in Rotr()
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| D | assembler_mips.h | 255 void Sll(Register rd, Register rt, int shamt);
256 void Srl(Register rd, Register rt, int shamt);
257 void Rotr(Register rd, Register rt, int shamt); // R2+
258 void Sra(Register rd, Register rt, int shamt);
266 void ShiftAndAdd(Register dst, Register src_idx, Register src_base, int shamt, Register tmp = AT);
1277 uint32_t EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);
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