Searched refs:BIT0 (Results 1 – 25 of 239) sorted by relevance
12345678910
85 #define B_PCH_LPC_COMMAND_IOSE BIT0 // I/O Space Enable142 #define B_PCH_LPC_ACPI_BASE_MEMI BIT0 // Memory Space Indication149 #define B_PCH_LPC_PMC_BASE_MEMI BIT0 // Memory Space Indication154 #define B_PCH_LPC_GPIO_BASE_MEMI BIT0 // Memory Space Indication161 #define B_PCH_LPC_IO_BASE_MEMI BIT0 // Memory Space Indication168 #define B_PCH_LPC_ILB_BASE_MEMI BIT0 // Memory Space Indication175 #define B_PCH_LPC_SPI_BASE_MEMI BIT0 // Memory Space Indicator182 #define B_PCH_LPC_MPHY_BASE_MEMI BIT0 // Memory Space Indicator189 #define B_PCH_LPC_PUNIT_BASE_MEMI BIT0 // Memory Space Indicator192 #define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable[all …]
64 #define B_PCH_SMBUS_PCICMD_IOSE BIT0 // I/O Space Enable68 #define B_PCH_SMBUS_BASE_IOSI BIT0 // IO Space Indicator86 #define B_PCH_SMBUS_HBSY BIT0 // Host Busy102 #define B_PCH_SMBUS_INTREN BIT0 // Interrupt Enable109 #define B_PCH_SMBUS_RW_SEL BIT0 // Direction of the host transfer, 1 = read, 0 = w…124 #define B_PCH_SMBUS_CRCE BIT0 // CRC Error128 #define B_PCH_SMBUS_AAC BIT0 // Automatically Append CRC133 #define B_PCH_SMBUS_SMLINK0_CUR_STS BIT0 // Not supported139 #define B_PCH_SMBUS_SMBCLK_CUR_STS BIT0 // SMBCLK Current Status142 #define B_PCH_SMBUS_HOST_NOTIFY_STS BIT0 // Host Notify Status[all …]
87 #define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space94 #define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space122 #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State172 #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space179 #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space207 #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State218 #define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset259 #define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space266 #define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space294 #define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State[all …]
77 #define B_PCH_SATA_COMMAND_IOSE BIT0 // I/O Space Enable96 #define B_PCH_SATA_PI_REGISTER_PNE BIT0 // Primary Mode Native Enable117 #define B_PCH_SATA_PCMD_BAR_RTE BIT0 // Resource Type Indicator121 #define B_PCH_SATA_PCTL_BAR_RTE BIT0 // Resource Type Indicator125 #define B_PCH_SATA_SCMD_BAR_RTE BIT0 // Resource Type Indicator129 #define B_PCH_SATA_SCTL_BAR_RTE BIT0 // Resource Type Indicator134 #define B_PCH_SATA_LBAR_RTE BIT0 // Resource Type Indicator146 #define B_PCH_SATA_ABAR_RTE BIT0 // Resource Type Indicator165 #define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State199 #define B_PCH_SATA_PCS_PORT0_EN BIT0 // Port 0 Enabled[all …]
72 #define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State74 #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State95 #define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)96 #define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
134 #define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC.146 #define OPTIONS_1_DMA_DISABLE (BIT0)226 #define CPU0_NON_SMM BIT0240 #define SMM_LOCKED (BIT0) // SMM Locked245 #define HMBOUND_LOCK BIT0284 #define B_STPDDRCFG_FORCE_RECOVERY BIT0315 #define B_TSCGF3_CONFIG_ITSRST BIT0329 #define B_CFG_STICKY_RW_SMM_VIOLATION BIT0398 #define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status446 #define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0)[all …]
53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) //…70 #define I2C_REG_RAW_INTR_STAT_RX_UNDER (BIT0) // Raw Interrupt Status Register RX Unde…81 #define B_I2C_REG_CLR_STOP_DET (BIT0) // Clear STOP DET Interrupt Register83 #define B_I2C_REG_CLR_START_DET (BIT0) // Clear START DET Interrupt Register85 #define B_I2C_REG_ENABLE (BIT0) // Enable (1) or disable (0) I2C Control…88 #define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register …90 #define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register b…
34 #define UART_FCR_FIFO_ENABLE BIT038 #define UART_LCR_CHAR_LENGTH_8 (BIT1 | BIT0)41 #define UART_MCR_DTR_FORCE_ACTIVE BIT046 #define UART_LSR_RX_FIFO_E_MASK BIT047 #define UART_LSR_RX_FIFO_E_NOT_EMPTY BIT0
61 #define GPIO_SYSCONFIG_AUTOIDLE_MASK BIT063 #define GPIO_SYSCONFIG_AUTOIDLE_ON BIT065 #define GPIO_SYSSTATUS_RESETDONE_MASK BIT067 #define GPIO_SYSSTATUS_RESETDONE_COMPLETE BIT087 #define GPIO_CTRL_DISABLEMODULE_MASK BIT089 #define GPIO_CTRL_DISABLEMODULE_DISABLE BIT0
56 #define TISR_MAT_IT_FLAG_MASK BIT066 #define TISR_MAT_IT_FLAG_CLEAR BIT071 #define TCLR_ST_ON BIT078 #define TIER_MAT_IT_ENABLE BIT0
27 #define RESETDONE_MASK BIT028 #define RESETDONE BIT034 #define OD BIT057 #define DE_ENABLE BIT079 #define CMDI_MASK BIT081 #define CMDI_NOT_ALLOWED BIT097 #define ICE BIT0112 #define CC BIT0123 #define CC_EN BIT0138 #define CC_SIGEN BIT0
29 #define TIMEOUTENABLE BIT057 #define OEONTIME BIT084 #define ECCENABLE BIT090 #define ECCPOINTER_REG1 BIT0
104 #define SOFT_RESET_CHECK_MAC_ADDR_LOAD BIT0116 #define PHY_RESET_PMT BIT0128 #define HW_CONF_USE_LEDS BIT0148 #define AUTO_NEGOTIATE_COLLISION_TEST BIT0166 #define STOP_TX_MAC BIT0178 #define STOP_RX_CLEAR BIT0188 #define START_TX_MAC BIT0200 #define START_RX_CLEAR BIT0239 #define ALLOC_USE_DEFAULT BIT0
34 #define SELECT_DRV BIT0 // Select Drive: 0=A 1=B42 #define MSR_DAB BIT0 // Drive A Busy51 #define CCR_DRC (BIT0 | BIT1) // Data Rate select106 #define STS0_US0 BIT0 // Unit Select0121 #define STS1_MA BIT0 // Missing Address Mark136 #define STS2_MD BIT0 // Missing Address Mark in DataField156 #define STS3_US0 BIT0 // Unit Select0
75 #define TCR_TXENA BIT090 #define EPHSR_TX_SUC BIT0105 #define RCR_RX_ABORT BIT0137 #define CTR_STORE BIT0150 #define MMUCR_BUSY BIT0183 #define IST_RCV BIT0192 #define MGMT_MDO BIT0203 #define RX_MULTICAST BIT0255 #define PHYSTS_EXT_CAP BIT0 // Extended Capabilities Regist…269 #define PHYANA_CSMA BIT0 // Advertise CSMA capability
32 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC0 BIT0 // LPSS DMA Disable52 #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space59 #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space68 #define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset86 #define B_MASTER_MODE BIT0118 #define I2C_INTR_RX_UNDER BIT0182 #define I2C_INTR_RX_UNDER BIT0
103 #define VRING_AVAIL_F_NO_INTERRUPT BIT0117 #define VRING_USED_F_NO_NOTIFY BIT0137 #define VRING_DESC_F_NEXT BIT0 // more descriptors in this request162 #define VSTAT_ACK BIT0
61 msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : (BIT11 | BIT10 | BIT9 | BIT8); in set_rcvn()62 tempD = (byte_lane & BIT0) ? ((pi_count / HALF_CLK) << 20) : ((pi_count / HALF_CLK) << 8); in set_rcvn()71 reg = (byte_lane & BIT0) ? (B1DLLPICODER0) : (B0DLLPICODER0); in set_rcvn()84 msk |= (byte_lane & BIT0) ? (BIT5) : (BIT2); in set_rcvn()90 msk |= (byte_lane & BIT0) ? (BIT11) : (BIT8); in set_rcvn()128 tempD >>= (byte_lane & BIT0) ? (20) : (8); in get_rcvn()137 reg = (byte_lane & BIT0) ? (B1DLLPICODER0) : (B0DLLPICODER0); in get_rcvn()170 reg = (byte_lane & BIT0) ? (B1RXDQSPICODE) : (B0RXDQSPICODE); in set_rdqs()172 msk = (BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0); in set_rdqs()205 reg = (byte_lane & BIT0) ? (B1RXDQSPICODE) : (B0RXDQSPICODE); in get_rdqs()[all …]
33 #define B_MASTER_MODE BIT065 #define I2C_INTR_RX_UNDER BIT0125 #define I2C_INTR_RX_UNDER BIT0129 #define B_PCH_LPIO_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
40 #define CARD_DETECT_ENABLE (BIT2 | BIT0) // GPIO ON + GPIO CD1 enabled44 #define CARD_DETECT_BIT BIT048 #define LEDAON BIT0