Searched refs:BIT1 (Results 1 – 25 of 214) sorted by relevance
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84 #define B_PCH_LPC_COMMAND_MSE BIT1 // Memory Space Enable141 #define B_PCH_LPC_ACPI_BASE_EN BIT1 // Enable Bit148 #define B_PCH_LPC_PMC_BASE_EN BIT1 // Enable Bit153 #define B_PCH_LPC_GPIO_BASE_EN BIT1 // Enable Bit160 #define B_PCH_LPC_IO_BASE_EN BIT1 // Enable Bit167 #define B_PCH_LPC_ILB_BASE_EN BIT1 // Enable Bit174 #define B_PCH_LPC_SPI_BASE_EN BIT1 // Enable Bit181 #define B_PCH_LPC_MPHY_BASE_EN BIT1 // Enable Bit188 #define B_PCH_LPC_PUNIT_BASE_EN BIT1 // Enable Bit207 #define B_PCH_LPC_FWH_BIOS_DEC_E50 BIT1 // 50-5F Enable[all …]
68 #define B_PCH_LPSS_DMAC_STSCMD_MSE BIT1 // Memory Space Enable86 #define B_PCH_LPSS_DMAC_BAR_TYPE (BIT2 | BIT1) // Type93 #define B_PCH_LPSS_DMAC_BAR1_TYPE (BIT2 | BIT1) // Type122 #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State153 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable171 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type178 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type207 #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State217 #define B_PCH_LPSS_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset240 #define B_PCH_LPSS_PWM_STSCMD_MSE BIT1 // Memory Space Enable[all …]
63 #define B_PCH_SMBUS_PCICMD_MSE BIT1 // Memory Space Enable85 #define B_PCH_SMBUS_INTR BIT1 // Interrupt101 #define B_PCH_SMBUS_KILL BIT1 // Kill127 #define B_PCH_SMBUS_E32B BIT1 // Enable 32-byte Buffer132 #define B_PCH_SMBUS_SMLINK1_CUR_STS BIT1 // Not supported138 #define B_PCH_SMBUS_SMBDATA_CUR_STS BIT1 // SMBDATA Current Status146 #define B_PCH_SMBUS_HOST_NOTIFY_WKEN BIT1 // Host Notify Wake Enable
72 #define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0) // Power State74 #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0) // D3 Hot State95 #define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)96 #define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)
76 #define B_PCH_SATA_COMMAND_MSE BIT1 // Memory Space Enable95 #define B_PCH_SATA_PI_REGISTER_PNC BIT1 // Primary Mode Native Capable145 #define B_PCH_SATA_ABAR_TP (BIT2 | BIT1) // Type165 #define B_PCH_SATA_PMCS_PS (BIT1 | BIT0) // Power State198 #define B_PCH_SATA_PCS_PORT1_EN BIT1 // Port 1 Enabled207 #define B_PCH_SATA_PORT1_IMPLEMENTED BIT1 // Port 1 Implemented
50 #define B_I2C_REG_CON_SPEED (BIT2+BIT1) // standard mode (01) or fast mode (10)53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) //…69 #define I2C_REG_RAW_INTR_STAT_RX_OVER (BIT1) // Raw Interrupt Status Register RX Over…88 #define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register …90 #define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register b…
239 #define SMM_READ_OPEN (BIT1) // SMM Reads OPEN330 #define B_CFG_STICKY_RW_HMB_VIOLATION BIT1397 #define B_QNC_SMBUS_DERR (BIT1) // Device Error497 #define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer512 #define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer545 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)568 #define B_QNC_LPC_BIOS_CNTL_BLE (BIT1)616 #define B_RST_CNT_WARM_RST (BIT1) // Warm reset654 #define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable684 #define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fata…[all …]
31 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC1 BIT1 // LPSS I2C #1 Disable45 #define B_PCH_LPSS_I2C_STSCMD_MSE BIT1 // Memory Space Enable51 #define B_PCH_LPSS_I2C_BAR_TYPE (BIT2 | BIT1) // Type58 #define B_PCH_LPSS_I2C_BAR1_TYPE (BIT2 | BIT1) // Type67 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset117 #define I2C_INTR_RX_OVER BIT1142 #define STAT_TFNF BIT1 // TX FIFO is not full181 #define I2C_INTR_RX_OVER BIT1
43 #define MSR_DBB BIT1 // Drive B Busy51 #define CCR_DRC (BIT0 | BIT1) // Data Rate select105 #define STS0_US1 BIT1 // Unit Select1120 #define STS1_NW BIT1 // Not Writable135 #define STS2_BC BIT1 // Bad Cylinder155 #define STS3_US1 BIT1 // Unit Select1
23 #define SOFTRESET BIT136 #define INIT BIT158 #define BCE_ENABLE BIT182 #define DATI_MASK BIT184 #define DATI_NOT_ALLOWED BIT188 #define DTW_4_BIT BIT198 #define ICS_MASK BIT199 #define ICS BIT1113 #define TC BIT1124 #define TC_EN BIT1[all …]
55 #define TISR_OVF_IT_FLAG_MASK BIT165 #define TISR_OVF_IT_FLAG_CLEAR BIT169 #define TCLR_AR_AUTORELOAD BIT176 #define TIER_OVF_IT_ENABLE BIT1
75 #define CM_FCLKEN_USBHOST_EN_USBHOST2_MASK BIT177 #define CM_FCLKEN_USBHOST_EN_USBHOST2_ENABLE BIT1153 #define CM_CLKSEL_PER_CLKSEL_GPT3_SYS BIT1159 #define RST_GS BIT1161 #define GLOBAL_SW_RST BIT1
33 #define UART_FCR_RX_FIFO_CLEAR BIT138 #define UART_LCR_CHAR_LENGTH_8 (BIT1 | BIT0)40 #define UART_MCR_RTS_FORCE_ACTIVE BIT1
25 #define NACK_IE BIT132 #define NACK BIT143 #define STP BIT1
105 #define SOFT_RESET_CLEAR_INT BIT1117 #define PHY_RESET_BCR BIT1149 #define AUTO_NEGOTIATE_ADVERTISE_ALL BIT1167 #define STOP_TX_CFG BIT1189 #define START_TX_CFG BIT1240 #define ALLOC_USE_FIFOS BIT1
64 #define I2C_INTR_RX_OVER BIT189 #define STAT_TFNF BIT1 // TX FIFO is not full124 #define I2C_INTR_RX_OVER BIT1128 #define B_PCH_LPIO_I2C_MEM_RESETS_FUNC BIT1 // Function Clock Domain Reset
76 #define TCR_LOOP BIT191 #define EPHSR_SNGLCOL BIT1106 #define RCR_PRMS BIT1138 #define CTR_RELOAD BIT1184 #define IST_TX BIT1193 #define MGMT_MDI BIT1256 #define PHYSTS_JABBER BIT1 // Jabber condition detected
43 #define ISP1761_DC_INTERRUPT_SOF BIT183 #define ISP1761_CTRL_FUNCTION_STATUS BIT199 #define ISP1761_OTG_CTRL_DP_PULLDOWN BIT1104 #define ISP1761_OTG_STATUS_A_B_SESS_VLD BIT1
50 #define USBPORTSC_CSC BIT1 // Connect Status Change71 #define USBCMD_HCRESET BIT1 // Host reset83 #define USBSTS_ERROR BIT1 // Interrupt due to error95 #define USBTD_BITSTUFF BIT1 // Bit stuff error
196 if (ErrorCode & BIT1) { in GetErrorReason()499 }while ((TimeOut2-- > 0) && (Data & BIT1)); in SendCommand()630 Data &= ~ (BIT5 | BIT1 | BIT2); in SendCommand()631 Data |= BIT1; // Enable block count always in SendCommand()634 Data |= (BIT5 | BIT1 | BIT2); in SendCommand()636 Data |= (BIT5 | BIT1); in SendCommand()669 Data = (CommandIndex << 8) | BIT1 | BIT4| BIT3; in SendCommand()675 Data = (CommandIndex << 8) | BIT0 | BIT1 | BIT4| BIT3; in SendCommand()686 Data = (CommandIndex << 8) | BIT1; in SendCommand()750 if ((Data & BIT1) == BIT1) { in SendCommand()[all …]