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Searched refs:BIT18 (Results 1 – 25 of 40) sorted by relevance

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/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dmeminit.c558 …DDRIODQ_CH_OFFSET)), tempD, ((BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
566 …BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
567 …BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
573 …BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
574 …BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
578 …FSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
579 …FSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
603 …1|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
604 …BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
605 …BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT1… in ddrphy_init()
[all …]
Dgeneral_definitions.h35 #undef BIT18
71 #define BIT18 0x00040000U macro
Dmeminit_utils.c237 msk = (byte_lane & BIT0) ? (BIT19 | BIT18 | BIT17 | BIT16) : (BIT7 | BIT6 | BIT5 | BIT4); in set_wdqs()
250 msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16); in set_wdqs()
472 …msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) | (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | B… in set_wcmd()
582 …msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) | (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BI… in set_wclk()
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
DOmap3530Dma.h63 #define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18
79 #define DMA4_CCR_FS_BLOCK (0 | BIT18)
81 #define DMA4_CCR_FS_PACKET (BIT5 | BIT18)
DOmap3530MMCHS.h129 #define CEB_EN BIT18
144 #define CEB_SIGEN BIT18
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
DOmap3530Dma.h63 #define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18
79 #define DMA4_CCR_FS_BLOCK (0 | BIT18)
81 #define DMA4_CCR_FS_PACKET (BIT5 | BIT18)
DOmap3530MMCHS.h129 #define CEB_EN BIT18
144 #define CEB_SIGEN BIT18
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
DBoardFeatures.h62 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
66 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18
156 #define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
160 #define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DQuarkNcSocId.h149 #define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18)
234 #define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN
295 #define B_TSCGF1_CONFIG_IBGCHOPEN BIT18
322 #define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18
657 #define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
DAhciMode.h20 #define EFI_AHCI_CAP_SAM BIT18
130 #define EFI_AHCI_PORT_CMD_HPCP BIT18
171 #define EFI_AHCI_PORT_SERR_CW BIT18
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
DLan9118DxeHw.h116 #define INSTS_PHY_INT BIT18 // Indicates PHY Interrupt
212 #define MACCR_PRMS BIT18 // Promiscuous Mode bit
258 #define GPIO_GPIO2_PUSH_PULL BIT18
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
DSP804Timer.h51 #define SP810_SYS_CTRL_TIMER1_EN BIT18
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
DPchRegsPcu.h555 #define B_PCH_SMI_EN_INTEL_USB2 BIT18 // Intel USB 2 Enable
587 #define B_PCH_SMI_STS_INTEL_USB2 BIT18 // Intel USB 2 Status
699 #define B_PCH_PMC_GEN_PMCON_MIN_SLP_S4 BIT18 // Minimum SLP_S4# Assertion Width Violatio…
727 #define B_PCH_PMC_GEN_PMCON_LOCK_S4_STRET_LD BIT18 // SLP_S3 / SLP_S4 Stretching Policy Lock-D…
760 #define B_PCH_PMC_FUNC_DIS_USB BIT18 // USB Disable
804 #define B_PCH_PMC_GPI_ROUT_9 (BIT19 | BIT18)
883 #define B_PCH_PMC_D3_STS_0_USB BIT18 // USB
920 #define B_PCH_PMC_D3_STDBY_STS_0_USB BIT18 // USB
DPchRegsPcie.h76 #define B_PCH_PCIE_SLCTL_SLSTS_MSC BIT18 // MRL Sensor Changed
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
DVirtioNet.h59 #define VIRTIO_NET_F_CTRL_RX BIT18 // control channel RX mode support
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
DCommonIncludes.h98 #define BIT18 0x00040000
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchRegs.h64 #define BIT18 0x00040000 macro
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
DIoh.h47 #define BIT18 0x00040000 macro
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
DPL180Mci.h101 #define MCI_STATUS_CMD_TXFIFOEMPTY BIT18
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/
DBaseTypes.h239 #define BIT18 0x00040000 macro
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
DXhciReg.h90 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
DXhciReg.h175 #define XHC_PORTSC_PEC BIT18 // Port Enabled/Disabled Change
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/
DSDController.c1327 if ((Data & (BIT16 | BIT17 | BIT18)) != (BIT16 | BIT17 | BIT18)) { in DetectCardAndInitHost()
1636 if ((Data & BIT18) != 0) { in SDControllerStart()
/device/linaro/bootloader/edk2/MdePkg/Include/Guid/
DCper.h772 #define EFI_PLATFORM_MEMORY_ERROR_EXTENDED_ROW_BIT_16_17_VALID BIT18
848 #define EFI_PLATFORM_MEMORY2_CARD_HANDLE_VALID BIT18
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/
DVlvCommonDefinitions.h95 #define BIT18 0x00040000 macro

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