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Searched refs:BIT21 (Results 1 – 25 of 41) sorted by relevance

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/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dgeneral_definitions.h38 #undef BIT21
74 #define BIT21 0x00200000U macro
Dmeminit.c566 …l_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
567 …l_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
573 …l_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
574 …l_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
578 …_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
579 …_i * DDRIODQ_CH_OFFSET)), (((tCAS+7)<<16)|((tCAS-4)<<8)|((tCWL-2)<<0)), ((BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
603 …xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
604 …616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
605 …xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
606 …xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|… in ddrphy_init()
[all …]
Dmeminit_utils.c61 msk = (byte_lane & BIT0) ? (BIT23 | BIT22 | BIT21 | BIT20) : (BIT11 | BIT10 | BIT9 | BIT8); in set_rcvn()
250 msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16); in set_wdqs()
472 …msk = (BIT29 | BIT28 | BIT27 | BIT26 | BIT25 | BIT24) | (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | B… in set_wcmd()
582 …msk = (BIT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) | (BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BI… in set_wclk()
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/
DOmap3530MMCHS.h69 #define DP_ENABLE BIT21
119 #define DCRC BIT21
132 #define DCRC_EN BIT21
147 #define DCRC_SIGEN BIT21
DOmap3530Dma.h72 #define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/
DOmap3530MMCHS.h69 #define DP_ENABLE BIT21
119 #define DCRC BIT21
132 #define DCRC_EN BIT21
147 #define DCRC_SIGEN BIT21
DOmap3530Dma.h72 #define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/
DThumbDisassembler.c759 W = (OpCode32 & BIT21) == BIT21; in DisassembleThumbInstruction()
814 W = (OpCode32 & BIT21) == BIT21; in DisassembleThumbInstruction()
851 W = (OpCode32 & BIT21) == BIT21; in DisassembleThumbInstruction()
857 W = (OpCode32 & BIT21) == BIT21; in DisassembleThumbInstruction()
927 if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) { in DisassembleThumbInstruction()
DArmDisassembler.c180 W = (OpCode & BIT21) == BIT21; in DisassembleArmInstruction()
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/
DPchRegsPcu.h423 #define B_PCH_ILB_DEF0_SDD BIT21 // Sub Decode Disable
653 #define B_PCH_TCO_CNT_OS_POLICY (BIT21 | BIT20) // OS Policy
685 #define B_PCH_PMC_PM_STS_PMC_MSG_2_FULL BIT21 // PMC 2 Message Full Status
696 #define B_PCH_PMC_GEN_PMCON_MEM_SR BIT21 // Memory Placed in Self-Refresh
756 #define B_PCH_PMC_FUNC_DIS_PCI_EX_FUNC1 BIT21 // PCI Express Function 1 Disable
788 #define B_PCH_PMC_PMIR_IGNORE_HPET BIT21 // Ignore HPET Disable Check Before Going t…
805 #define B_PCH_PMC_GPI_ROUT_10 (BIT21 | BIT20)
881 #define B_PCH_PMC_D3_STS_0_PCIEF1 BIT21 // PCIe Function 1
918 #define B_PCH_PMC_D3_STDBY_STS_0_PCIEF1 BIT21 // PCIe Function 1
DPchRegsPcie.h74 #define B_PCH_PCIE_SLCTL_SLSTS_MS BIT21 // MRL Sensor State
/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
DSP804Timer.h54 #define SP810_SYS_CTRL_TIMER3_TIMCLK BIT21 // 0=REFCLK, 1=TIMCLK
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
DPeImage.h314 #define EFI_IMAGE_SCN_ALIGN_2BYTES BIT21 ///< 0x00200000
315 #define EFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) ///< 0x00300000
318 #define EFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) ///< 0x00600000
319 #define EFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) ///< 0x00700000
/device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi6220/Include/
DHi6220.h34 #define CTRL4_OTG_PHY_SEL BIT21
/device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/
DVirtioNet.h61 #define VIRTIO_NET_F_GUEST_ANNOUNCE BIT21 // guest can send gratuitous pkts
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/
DCommonIncludes.h95 #define BIT21 0x00200000
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/
DBoardFeatures.h69 #define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
163 #define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/
DAhciMode.h133 #define EFI_AHCI_PORT_CMD_ESP BIT21
174 #define EFI_AHCI_PORT_SERR_CRCE BIT21
/device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/
DLan9118DxeHw.h119 #define INSTS_TX_IOC BIT21 // Finished loading IOC flagg…
215 #define MACCR_LOOPBK BIT21 // Loopback operation mode bit
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
DXhciReg.h93 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
107 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
DXhciReg.h178 #define XHC_PORTSC_PRC BIT21 // Port Reset Change
192 #define XHC_HUB_PORTSC_BHRC BIT21 // Hub's Port Warm Reset Change
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchRegs.h67 #define BIT21 0x00200000 macro
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Include/
DIoh.h50 #define BIT21 0x00200000 macro
/device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/
DPL180Mci.h104 #define MCI_STATUS_CMD_RXDATAAVAILBL BIT21
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/
DBaseTypes.h242 #define BIT21 0x00200000 macro

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