Searched refs:BIT3 (Results 1 – 25 of 140) sorted by relevance
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85 #define B_PCH_LPSS_DMAC_BAR_PF BIT3 // Prefetchable92 #define B_PCH_LPSS_DMAC_BAR1_PF BIT3 // Prefetchable121 #define B_PCH_LPSS_DMAC_PCS_NSS BIT3 // No Soft Reset170 #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable177 #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable206 #define B_PCH_LPSS_I2C_PCS_NSS BIT3 // No Soft Reset257 #define B_PCH_LPSS_PWM_BAR_PF BIT3 // Prefetchable264 #define B_PCH_LPSS_PWM_BAR1_PF BIT3 // Prefetchable293 #define B_PCH_LPSS_PWM_PCS_NSS BIT3 // No Soft Reset344 #define B_PCH_LPSS_HSUART_BAR_PF BIT3 // Prefetchable[all …]
82 #define B_PCH_LPC_COMMAND_SCE BIT3 // Special Cycle Enable98 #define B_PCH_LPC_DEV_STS_INT_STS BIT3 // Interrupt Status146 #define B_PCH_LPC_PMC_BASE_PREF BIT3 // Prefetchable158 #define B_PCH_LPC_IO_BASE_PREF BIT3 // Prefetchable165 #define B_PCH_LPC_ILB_BASE_PREF BIT3 // Prefetchable172 #define B_PCH_LPC_SPI_BASE_PREF BIT3 // Prefetchable179 #define B_PCH_LPC_MPHY_BASE_PREF BIT3 // Prefetchable186 #define B_PCH_LPC_PUNIT_BASE_PREF BIT3 // Prefetchable205 #define B_PCH_LPC_FWH_BIOS_DEC_E70 BIT3 // 70-7F Enable260 #define B_PCH_ILB_MC_DRTC BIT3 // Disable RTC[all …]
74 #define B_PCH_SATA_COMMAND_SCE BIT3 // Special Cycle Enable88 #define B_PCH_SATA_PCISTS_ITNS BIT3 // Interrupt Status93 #define B_PCH_SATA_PI_REGISTER_SNC BIT3 // Secondary Mode Native Capable144 #define B_PCH_SATA_ABAR_PF BIT3 // Prefetchable162 #define B_PCH_SATA_PMCS_NSFRST BIT3 // No Soft Reset196 #define B_PCH_SATA_PCS_PORT3_EN BIT3 // Port 3 Enabled205 #define B_PCH_SATA_PORT3_IMPLEMENTED BIT3 // Port 3 Implemented
50 #define B_PCH_SPI_HSFS_BERASE_MASK (BIT4 | BIT3) // Block / Sector Erase Size82 #define B_PCH_SPI_OPTYPE1_MASK (BIT3 | BIT2) // Opcode Type 1 Mask110 #define B_PCH_SPI_BCR_SRC (BIT3 | BIT2) // SPI Read Configuration (SRC)
53 #define B_I2C_REG_TAR (BIT9+BIT8+BIT7+BIT6+BIT5+BIT4+BIT3+BIT2+BIT1+BIT0) //…68 #define I2C_REG_RAW_INTR_STAT_TX_OVER (BIT3) // Raw Interrupt Status Register TX Over…88 #define B_I2C_REG_TXFLR (BIT3+BIT2+BIT1+BIT0) // Transmit FIFO Level Register …90 #define B_I2C_REG_RXFLR (BIT3+BIT2+BIT1+BIT0) // Receive FIFO Level Register b…
237 #define SMM_CTL_EN (BIT3) // SMM enable289 #define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3)332 #define B_CFG_STICKY_RW_DECC_VIOLATION BIT3510 #define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI545 #define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0)615 #define B_RST_CNT_COLD_RST (BIT3) // Cold reset652 #define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable675 #define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable679 #define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS …682 #define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable[all …]
29 #define B_PCH_PMC_FUNC_DIS_LPSS_FUNC3 BIT3 // LPSS PCM Disable50 #define B_PCH_LPSS_I2C_BAR_PF BIT3 // Prefetchable57 #define B_PCH_LPSS_I2C_BAR1_PF BIT3 // Prefetchable115 #define I2C_INTR_TX_OVER BIT3140 #define STAT_RFNE BIT3 // RX FIFO is not empty179 #define I2C_INTR_TX_OVER BIT3
52 #define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change73 #define USBCMD_EGSM BIT3 // Global Suspend Mode85 #define USBSTS_HSE BIT3 // Host System Error93 #define USBTD_NAK BIT3 // NAK is received
153 #define EFI_ERROR_SECTION_FLAGS_ERROR_THRESHOLD_EXCEEDED BIT3229 #define EFI_GENERIC_ERROR_PROC_OPERATION_VALID BIT3283 #define EFI_GENERIC_ERROR_PROC_FLAGS_CORRECTED BIT3343 #define EFI_CACHE_CHECK_CONTEXT_CORRUPT_VALID BIT3396 #define EFI_TLB_CHECK_CONTEXT_CORRUPT_VALID BIT3447 #define EFI_BUS_CHECK_CONTEXT_CORRUPT_VALID BIT3522 #define EFI_MS_CHECK_PRECISE_IP_VALID BIT3570 #define EFI_IA32_X64_ERROR_PROC_RESPONDER_ID_VALID BIT3757 #define EFI_PLATFORM_MEMORY_NODE_VALID BIT3833 #define EFI_PLATFORM_MEMORY2_NODE_VALID BIT3[all …]
62 #define I2C_INTR_TX_OVER BIT387 #define STAT_RFNE BIT3 // RX FIFO is not empty122 #define I2C_INTR_TX_OVER BIT3
45 #define ISP1761_DC_INTERRUPT_SUSP BIT371 #define ISP1761_ENDPOINT_TYPE_ENABLE BIT381 #define ISP1761_CTRL_FUNCTION_VENDP BIT3
56 #define HDLCD_UNDERRUN BIT3 /* No Data available while DATAEN active */66 #define HDLCD_BURST_8 BIT373 #define HDLCD_DATA_HIGH BIT3
35 #define SP804_TIMER_CTRL_PRESCALE_MASK (BIT3|BIT2)38 #define SP804_PRESCALE_DIV_256 BIT3
28 #define UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY BIT338 #define UHH_HOSTCONFIG_ENA_INCR8_ENABLE BIT3
23 #define RRDY_IE BIT330 #define RRDY BIT3
93 #define EPHSR_LTX_MULT BIT3119 #define RPCR_LS1B BIT3186 #define IST_ALLOC BIT3195 #define MGMT_MDOE BIT3258 #define PHYSTS_AUTO_CAP BIT3 // Auto-Negotiation Capability
29 #define CTRL4_FPGA_EXT_PHY_SEL BIT338 #define CTRL5_USBOTG_RES_SEL BIT3
60 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable64 #define XHC_USBSTS_EINT BIT3 // Event Interrupt77 #define XHC_CRCR_CRR BIT3 // Command Ring Running83 #define XHC_PORTSC_OCA BIT3 // Over-current Active100 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
116 #define IDE_SECONDARY_PROGRAMMABLE_INDICATOR BIT3122 #define BMIC_NREAD BIT3294 #define DTE0 BIT3
145 #define XHC_USBCMD_HSEE BIT3 // Host System Error Enable149 #define XHC_USBSTS_EINT BIT3 // Event Interrupt162 #define XHC_CRCR_CRR BIT3 // Command Ring Running168 #define XHC_PORTSC_OCA BIT3 // Over-current Active185 #define XHC_HUB_PORTSC_OCA BIT3 // Hub's Over-current Active
38 #define MCH_SMRAM_G_SMRAME BIT345 #define MCH_ESMRAMC_SM_L2 BIT3
73 #define I2C_INTR_TX_OVER BIT398 #define STAT_RFNE BIT3 // RX FIFO is not empty135 #define I2C_INTR_TX_OVER BIT3
20 #undef BIT356 #define BIT3 0x00000008U macro