Searched refs:CSSELR (Results 1 – 6 of 6) sorted by relevance
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Common/ |
| D | ArmLibPrivate.h | 72 IN UINT32 CSSELR
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| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/ArmV7/ |
| D | ArmLibSupportV7.asm | 84 mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
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| D | ArmLibSupportV7.S | 99 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
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| D | ArmV7Support.asm | 188 …mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for In…
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| D | ArmV7Support.S | 226 …mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for In…
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| /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/ |
| D | core_cm7.h | 435 …__IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register … member
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