| /device/linaro/bootloader/edk2/NetworkPkg/HttpBootDxe/ |
| D | HttpBootClient.c | 467 IN HTTP_BOOT_CACHE_CONTENT *Cache in HttpBootFreeCache() argument
475 if (Cache != NULL) { in HttpBootFreeCache()
479 if (Cache->RequestData != NULL) { in HttpBootFreeCache()
480 if (Cache->RequestData->Url != NULL) { in HttpBootFreeCache()
481 FreePool (Cache->RequestData->Url); in HttpBootFreeCache()
483 FreePool (Cache->RequestData); in HttpBootFreeCache()
489 if (Cache->ResponseData != NULL) { in HttpBootFreeCache()
490 if (Cache->ResponseData->Headers != NULL) { in HttpBootFreeCache()
491 for (Index = 0; Index < Cache->ResponseData->HeaderCount; Index++) { in HttpBootFreeCache()
492 FreePool (Cache->ResponseData->Headers[Index].FieldName); in HttpBootFreeCache()
[all …]
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| D | HttpBootClient.h | 57 HTTP_BOOT_CACHE_CONTENT *Cache; member
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| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/ |
| D | IsaFloppyBlock.c | 300 if (FdcDev->Cache != NULL) { in FddReadWriteBlocks()
303 CopyMem ((UINT8 *) Buffer, (UINT8 *) FdcDev->Cache, BlockSize); in FddReadWriteBlocks()
351 if (Lba0 == 0 && FdcDev->Cache == NULL) { in FddReadWriteBlocks()
352 FdcDev->Cache = AllocateCopyPool (BlockSize, Buffer); in FddReadWriteBlocks()
371 if (FdcDev->Cache != NULL) { in FdcFreeCache()
372 FreePool (FdcDev->Cache); in FdcFreeCache()
373 FdcDev->Cache = NULL; in FdcFreeCache()
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| D | IsaFloppy.c | 244 FdcDev->Cache = NULL; in FdcControllerDriverStart()
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| D | IsaFloppy.h | 80 UINT8 *Cache; member
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| /device/linaro/bootloader/edk2/MdePkg/Library/BaseCacheMaintenanceLib/ |
| D | BaseCacheMaintenanceLib.uni | 2 // Instance of Cache Maintenance Library using Base Library services.
4 // Cache Maintenance Library that uses Base Library services to maintain caches.
20 #string STR_MODULE_ABSTRACT #language en-US "Instance of Cache Maintenance Library usin…
22 #string STR_MODULE_DESCRIPTION #language en-US "The Cache Maintenance Library that uses Ba…
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| D | BaseCacheMaintenanceLib.inf | 2 # Instance of Cache Maintenance Library using Base Library services.
4 # Cache Maintenance Library that uses Base Library services to maintain caches.
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| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/ |
| D | Atapi.c | 1749 if (IdeBlkIoDevice->Cache != NULL) { in AtapiBlkIoReadBlocks()
1750 gBS->FreePool (IdeBlkIoDevice->Cache); in AtapiBlkIoReadBlocks()
1751 IdeBlkIoDevice->Cache = NULL; in AtapiBlkIoReadBlocks()
1766 if (IdeBlkIoDevice->Cache != NULL) { in AtapiBlkIoReadBlocks()
1767 gBS->FreePool (IdeBlkIoDevice->Cache); in AtapiBlkIoReadBlocks()
1768 IdeBlkIoDevice->Cache = NULL; in AtapiBlkIoReadBlocks()
1776 if (IdeBlkIoDevice->Cache != NULL) { in AtapiBlkIoReadBlocks()
1777 gBS->FreePool (IdeBlkIoDevice->Cache); in AtapiBlkIoReadBlocks()
1778 IdeBlkIoDevice->Cache = NULL; in AtapiBlkIoReadBlocks()
1815 if (Lba == 0 && (IdeBlkIoDevice->Cache == NULL)) { in AtapiBlkIoReadBlocks()
[all …]
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| D | Ide.c | 1183 if (IdeBlkIoDevice->Cache != NULL) { in ReleaseIdeResources()
1184 gBS->FreePool (IdeBlkIoDevice->Cache); in ReleaseIdeResources()
1185 IdeBlkIoDevice->Cache = NULL; in ReleaseIdeResources()
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| D | IdeBus.h | 100 UINT8 *Cache; member
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| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/ArmV7/ |
| D | ArmLibSupportV7.asm | 84 mcr p15,2,r0,c0,c0,0 ; Write Cache Size Selection Register (CSSELR)
86 mrc p15,1,r0,c0,c0,0 ; Read current CP15 Cache Size ID Register (CCSIDR)
94 mrc p15,1,r0,c0,c0,1 ; Read CP15 Cache Level ID Register
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| D | ArmLibSupportV7.S | 99 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
101 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
109 mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
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| D | ArmV7Support.asm | 89 bic r0, r0, #CTRL_C_BIT ; Disable D Cache
90 bic r0, r0, #CTRL_I_BIT ; Disable I Cache
102 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
111 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
178 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
184 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
188 …mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for In…
190 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
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| D | ArmV7Support.S | 126 bic r0, r0, #CTRL_C_BIT @ Disable D Cache
127 bic r0, r0, #CTRL_I_BIT @ Disable I Cache
216 mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
222 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
226 …mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for In…
228 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
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| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/Network/Ip4Dxe/ |
| D | Ip4Route.c | 213 Ip4InitRouteCache (&RtTable->Cache); in Ip4CreateRouteTable()
253 Ip4CleanRouteCache (&RtTable->Cache); in Ip4FreeRouteTable()
390 Ip4PurgeRouteCache (&RtTable->Cache, (UINTN) RtEntry); in Ip4DelRoute()
430 NET_LIST_FOR_EACH (Entry, &RtTable->Cache.CacheBucket[Index]) { in Ip4FindRouteCache()
513 IP4_ROUTE_CACHE_ENTRY *Cache; in Ip4Route() local
520 Head = &RtTable->Cache.CacheBucket[IP4_ROUTE_CACHE_HASH (Dest, Src)]; in Ip4Route()
578 Cache = NET_LIST_USER_STRUCT (Entry, IP4_ROUTE_CACHE_ENTRY, Link); in Ip4Route()
581 Ip4FreeRouteCacheEntry (Cache); in Ip4Route()
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| D | Ip4Route.h | 88 IP4_ROUTE_CACHE Cache; member
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| /device/linaro/bootloader/edk2/NetworkPkg/Ip6Dxe/ |
| D | Ip6Route.c | 242 NET_LIST_FOR_EACH (Entry, &RtTable->Cache.CacheBucket[Index]) { in Ip6FindRouteCache()
354 InitializeListHead (&RtTable->Cache.CacheBucket[Index]); in Ip6CreateRouteTable()
355 RtTable->Cache.CacheNum[Index] = 0; in Ip6CreateRouteTable()
397 NET_LIST_FOR_EACH_SAFE (Entry, Next, &RtTable->Cache.CacheBucket[Index]) { in Ip6CleanRouteTable()
540 Ip6PurgeRouteCache (&RtTable->Cache, (UINTN) Route); in Ip6DelRoute()
585 ListHead = &RtTable->Cache.CacheBucket[Index]; in Ip6Route()
631 RtTable->Cache.CacheNum[Index]++; in Ip6Route()
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| D | Ip6Route.h | 66 IP6_ROUTE_CACHE Cache; member
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| /device/linaro/bootloader/edk2/NetworkPkg/UefiPxeBcDxe/ |
| D | PxeBcBoot.c | 68 PXEBC_DHCP_PACKET_CACHE *Cache; in PxeBcSelectBootPrompt() local
85 Cache = Mode->ProxyOfferReceived ? &Private->ProxyOffer : &Private->DhcpAck; in PxeBcSelectBootPrompt()
86 OfferType = Mode->UsingIpv6 ? Cache->Dhcp6.OfferType : Cache->Dhcp4.OfferType; in PxeBcSelectBootPrompt()
100 VendorOpt = &Cache->Dhcp4.VendorOpt; in PxeBcSelectBootPrompt()
108 Cache->Dhcp4.OptList[PXEBC_DHCP4_TAG_INDEX_BOOTFILE] != NULL) { in PxeBcSelectBootPrompt()
276 PXEBC_DHCP_PACKET_CACHE *Cache; in PxeBcSelectBootMenu() local
296 Cache = Mode->ProxyOfferReceived ? &Private->ProxyOffer : &Private->DhcpAck; in PxeBcSelectBootMenu()
297 OfferType = Mode->UsingIpv6 ? Cache->Dhcp6.OfferType : Cache->Dhcp4.OfferType; in PxeBcSelectBootMenu()
305 VendorOpt = &Cache->Dhcp4.VendorOpt; in PxeBcSelectBootMenu()
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| /device/linaro/bootloader/edk2/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/ |
| D | SecCarInit.s | 22 # Description: This function initializes the Cache for Data, Stack, and Code
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| D | SecCarInit.asm | 34 ; Description: This function initializes the Cache for Data, Stack, and Code
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| /device/linaro/bootloader/edk2/BeagleBoardPkg/Sec/ |
| D | Sec.inf | 30 Cache.c
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/TexasInstruments/BeagleBoard/Sec/ |
| D | Sec.inf | 30 Cache.c
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| /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/Edit/ |
| D | FileBuffer.c | 1446 CHAR8 *Cache; in FileBufferSave() local
1527 Cache = AllocateZeroPool (TotalSize); in FileBufferSave()
1528 if (Cache == NULL) { in FileBufferSave()
1539 Ptr = Cache; in FileBufferSave()
1568 Status = ShellWriteFile (FileHandle, &Size, Cache); in FileBufferSave()
1571 FreePool (Cache); in FileBufferSave()
1574 Ptr = Cache; in FileBufferSave()
1611 Status = ShellWriteFile (FileHandle, &Size, Cache); in FileBufferSave()
1614 FreePool (Cache); in FileBufferSave()
1619 FreePool (Cache); in FileBufferSave()
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| /device/linaro/bootloader/OpenPlatformPkg/Platforms/ARM/VExpress/AcpiTables/rtsm_ve-aemv8a/ |
| D | facp.asl | 74 [0002] CPU Cache Size : 0000
75 [0002] Cache Flush Stride : 0000
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