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Searched refs:DDRIOCCC_CH_OFFSET (Results 1 – 3 of 3) sorted by relevance

/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dmeminit_utils.c452 reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); in set_wcmd()
470 reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); in set_wcmd()
478 reg = CMDDLLPICODER0 + (channel * DDRIOCCC_CH_OFFSET); // PO in set_wcmd()
484 reg = CMDCFGREG0 + (channel * DDRIOCCC_CH_OFFSET); in set_wcmd()
524 reg = CMDPTRREG + (channel * DDRIOCCC_CH_OFFSET); in get_wcmd()
541 reg = CMDDLLPICODER1 + (channel * DDRIOCCC_CH_OFFSET); in get_wcmd()
569 reg = CCPTRREG + (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
581 reg += (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
586 reg += (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
589 reg += (channel * DDRIOCCC_CH_OFFSET); in set_wclk()
[all …]
Dmeminit.c520 …isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT20, BIT20); // SPID_INIT_CO… in ddrphy_init()
522 … isbM32m(DDRPHY, (CMDCFGREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT2, BIT2); // IOBUFACTRST_N=0 in ddrphy_init()
524 isbM32m(DDRPHY, (CMDPTRREG + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT0, BIT0); // WRPTRENABLE=0 in ddrphy_init()
594 isbM32m(DDRPHY, (CMDOBSCKEBBCTL + (channel_i * DDRIOCCC_CH_OFFSET)), 0, (BIT23)); in ddrphy_init()
597 isbM32m(DDRPHY, (CMDCFGREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), 0, (BIT1|BIT0)); in ddrphy_init()
600 …isbM32m(DDRPHY, (CMDRCOMPODT + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x03<<5)|(0x03<<0)), ((BIT9|BI… in ddrphy_init()
603 …isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((… in ddrphy_init()
604 …isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<1… in ddrphy_init()
605 …isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<… in ddrphy_init()
606 …isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<… in ddrphy_init()
[all …]
Dgen5_iosf_sb_definitions.h470 #define DDRIOCCC_CH_OFFSET 0x0800 macro