Home
last modified time | relevance | path

Searched refs:DHCSR (Results 1 – 4 of 4) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm3.h1154 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_sc300.h1134 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_cm4.h1300 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member
Dcore_cm7.h1487 …__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status … member