1 /** @file
2 
3   Copyright (c) 2015-2016, Linaro Limited. All rights reserved.
4 
5   This program and the accompanying materials
6   are licensed and made available under the terms and conditions of the BSD License
7   which accompanies this distribution.  The full text of the license may be found at
8   http://opensource.org/licenses/bsd-license.php
9 
10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 
13 **/
14 
15 #ifndef __DWCHW_H__
16 #define __DWCHW_H__
17 
18 #define HSOTG_REG(x)    (x)
19 
20 #define HCCHAR(_ch)                     HSOTG_REG(0x0500 + 0x20 * (_ch))
21 #define HCSPLT(_ch)                     HSOTG_REG(0x0504 + 0x20 * (_ch))
22 #define HCINT(_ch)                      HSOTG_REG(0x0508 + 0x20 * (_ch))
23 #define HCINTMSK(_ch)                   HSOTG_REG(0x050c + 0x20 * (_ch))
24 #define HCTSIZ(_ch)                     HSOTG_REG(0x0510 + 0x20 * (_ch))
25 #define HCDMA(_ch)                      HSOTG_REG(0x0514 + 0x20 * (_ch))
26 #define HCDMAB(_ch)                     HSOTG_REG(0x051c + 0x20 * (_ch))
27 
28 #define HCFG                            HSOTG_REG(0x0400)
29 #define HFIR                            HSOTG_REG(0x0404)
30 #define HFNUM                           HSOTG_REG(0x0408)
31 #define HPTXSTS                         HSOTG_REG(0x0410)
32 #define HAINT                           HSOTG_REG(0x0414)
33 #define HAINTMSK                        HSOTG_REG(0x0418)
34 #define HFLBADDR                        HSOTG_REG(0x041c)
35 
36 #define GOTGCTL                         HSOTG_REG(0x000)
37 #define GOTGINT                         HSOTG_REG(0x004)
38 #define GAHBCFG                         HSOTG_REG(0x008)
39 #define GUSBCFG                         HSOTG_REG(0x00C)
40 #define GRSTCTL                         HSOTG_REG(0x010)
41 #define GINTSTS                         HSOTG_REG(0x014)
42 #define GINTMSK                         HSOTG_REG(0x018)
43 #define GRXSTSR                         HSOTG_REG(0x01C)
44 #define GRXSTSP                         HSOTG_REG(0x020)
45 #define GRXFSIZ                         HSOTG_REG(0x024)
46 #define GNPTXFSIZ                       HSOTG_REG(0x028)
47 #define GNPTXSTS                        HSOTG_REG(0x02C)
48 #define GI2CCTL                         HSOTG_REG(0x0030)
49 #define GPVNDCTL                        HSOTG_REG(0x0034)
50 #define GGPIO                           HSOTG_REG(0x0038)
51 #define GUID                            HSOTG_REG(0x003c)
52 #define GSNPSID                         HSOTG_REG(0x0040)
53 #define GHWCFG1                         HSOTG_REG(0x0044)
54 #define GHWCFG2                         HSOTG_REG(0x0048)
55 #define GHWCFG3                         HSOTG_REG(0x004c)
56 #define GHWCFG4                         HSOTG_REG(0x0050)
57 #define GLPMCFG                         HSOTG_REG(0x0054)
58 #define HPTXFSIZ                        HSOTG_REG(0x100)
59 #define DPTXFSIZN(_a)                   HSOTG_REG(0x104 + (((_a) - 1) * 4))
60 #define HPRT0                           HSOTG_REG(0x0440)
61 #define PCGCCTL				HSOTG_REG(0xE00)
62 
63 #define DWC2_GOTGCTL_SESREQSCS				(1 << 0)
64 #define DWC2_GOTGCTL_SESREQSCS_OFFSET			0
65 #define DWC2_GOTGCTL_SESREQ				(1 << 1)
66 #define DWC2_GOTGCTL_SESREQ_OFFSET			1
67 #define DWC2_GOTGCTL_HSTNEGSCS				(1 << 8)
68 #define DWC2_GOTGCTL_HSTNEGSCS_OFFSET			8
69 #define DWC2_GOTGCTL_HNPREQ				(1 << 9)
70 #define DWC2_GOTGCTL_HNPREQ_OFFSET			9
71 #define DWC2_GOTGCTL_HSTSETHNPEN			(1 << 10)
72 #define DWC2_GOTGCTL_HSTSETHNPEN_OFFSET			10
73 #define DWC2_GOTGCTL_DEVHNPEN				(1 << 11)
74 #define DWC2_GOTGCTL_DEVHNPEN_OFFSET			11
75 #define DWC2_GOTGCTL_CONIDSTS				(1 << 16)
76 #define DWC2_GOTGCTL_CONIDSTS_OFFSET			16
77 #define DWC2_GOTGCTL_DBNCTIME				(1 << 17)
78 #define DWC2_GOTGCTL_DBNCTIME_OFFSET			17
79 #define DWC2_GOTGCTL_ASESVLD				(1 << 18)
80 #define DWC2_GOTGCTL_ASESVLD_OFFSET			18
81 #define DWC2_GOTGCTL_BSESVLD				(1 << 19)
82 #define DWC2_GOTGCTL_BSESVLD_OFFSET			19
83 #define DWC2_GOTGCTL_OTGVER				(1 << 20)
84 #define DWC2_GOTGCTL_OTGVER_OFFSET			20
85 #define DWC2_GOTGINT_SESENDDET				(1 << 2)
86 #define DWC2_GOTGINT_SESENDDET_OFFSET			2
87 #define DWC2_GOTGINT_SESREQSUCSTSCHNG			(1 << 8)
88 #define DWC2_GOTGINT_SESREQSUCSTSCHNG_OFFSET		8
89 #define DWC2_GOTGINT_HSTNEGSUCSTSCHNG			(1 << 9)
90 #define DWC2_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET		9
91 #define DWC2_GOTGINT_RESERVER10_16_MASK			(0x7F << 10)
92 #define DWC2_GOTGINT_RESERVER10_16_OFFSET		10
93 #define DWC2_GOTGINT_HSTNEGDET				(1 << 17)
94 #define DWC2_GOTGINT_HSTNEGDET_OFFSET			17
95 #define DWC2_GOTGINT_ADEVTOUTCHNG			(1 << 18)
96 #define DWC2_GOTGINT_ADEVTOUTCHNG_OFFSET		18
97 #define DWC2_GOTGINT_DEBDONE				(1 << 19)
98 #define DWC2_GOTGINT_DEBDONE_OFFSET			19
99 #define DWC2_GAHBCFG_GLBLINTRMSK			(1 << 0)
100 #define DWC2_GAHBCFG_GLBLINTRMSK_OFFSET			0
101 #define DWC2_GAHBCFG_HBURSTLEN_SINGLE			(0 << 1)
102 #define DWC2_GAHBCFG_HBURSTLEN_INCR			(1 << 1)
103 #define DWC2_GAHBCFG_HBURSTLEN_INCR4			(3 << 1)
104 #define DWC2_GAHBCFG_HBURSTLEN_INCR8			(5 << 1)
105 #define DWC2_GAHBCFG_HBURSTLEN_INCR16			(7 << 1)
106 #define DWC2_GAHBCFG_HBURSTLEN_MASK			(0xF << 1)
107 #define DWC2_GAHBCFG_HBURSTLEN_OFFSET			1
108 #define DWC2_GAHBCFG_DMAENABLE				(1 << 5)
109 #define DWC2_GAHBCFG_DMAENABLE_OFFSET			5
110 #define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL		(1 << 7)
111 #define DWC2_GAHBCFG_NPTXFEMPLVL_TXFEMPLVL_OFFSET	7
112 #define DWC2_GAHBCFG_PTXFEMPLVL				(1 << 8)
113 #define DWC2_GAHBCFG_PTXFEMPLVL_OFFSET			8
114 #define DWC2_GUSBCFG_TOUTCAL_MASK			(0x7 << 0)
115 #define DWC2_GUSBCFG_TOUTCAL_OFFSET			0
116 #define DWC2_GUSBCFG_PHYIF				(1 << 3)
117 #define DWC2_GUSBCFG_PHYIF_OFFSET			3
118 #define DWC2_GUSBCFG_ULPI_UTMI_SEL			(1 << 4)
119 #define DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET		4
120 #define DWC2_GUSBCFG_FSINTF				(1 << 5)
121 #define DWC2_GUSBCFG_FSINTF_OFFSET			5
122 #define DWC2_GUSBCFG_PHYSEL				(1 << 6)
123 #define DWC2_GUSBCFG_PHYSEL_OFFSET			6
124 #define DWC2_GUSBCFG_DDRSEL				(1 << 7)
125 #define DWC2_GUSBCFG_DDRSEL_OFFSET			7
126 #define DWC2_GUSBCFG_SRPCAP				(1 << 8)
127 #define DWC2_GUSBCFG_SRPCAP_OFFSET			8
128 #define DWC2_GUSBCFG_HNPCAP				(1 << 9)
129 #define DWC2_GUSBCFG_HNPCAP_OFFSET			9
130 #define DWC2_GUSBCFG_USBTRDTIM_MASK			(0xF << 10)
131 #define DWC2_GUSBCFG_USBTRDTIM_OFFSET			10
132 #define DWC2_GUSBCFG_NPTXFRWNDEN			(1 << 14)
133 #define DWC2_GUSBCFG_NPTXFRWNDEN_OFFSET			14
134 #define DWC2_GUSBCFG_PHYLPWRCLKSEL			(1 << 15)
135 #define DWC2_GUSBCFG_PHYLPWRCLKSEL_OFFSET		15
136 #define DWC2_GUSBCFG_OTGUTMIFSSEL			(1 << 16)
137 #define DWC2_GUSBCFG_OTGUTMIFSSEL_OFFSET		16
138 #define DWC2_GUSBCFG_ULPI_FSLS				(1 << 17)
139 #define DWC2_GUSBCFG_ULPI_FSLS_OFFSET			17
140 #define DWC2_GUSBCFG_ULPI_AUTO_RES			(1 << 18)
141 #define DWC2_GUSBCFG_ULPI_AUTO_RES_OFFSET		18
142 #define DWC2_GUSBCFG_ULPI_CLK_SUS_M			(1 << 19)
143 #define DWC2_GUSBCFG_ULPI_CLK_SUS_M_OFFSET		19
144 #define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV			(1 << 20)
145 #define DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV_OFFSET		20
146 #define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR		(1 << 21)
147 #define DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR_OFFSET	21
148 #define DWC2_GUSBCFG_TERM_SEL_DL_PULSE			(1 << 22)
149 #define DWC2_GUSBCFG_TERM_SEL_DL_PULSE_OFFSET		22
150 #define DWC2_GUSBCFG_IC_USB_CAP				(1 << 26)
151 #define DWC2_GUSBCFG_IC_USB_CAP_OFFSET			26
152 #define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE		(1 << 27)
153 #define DWC2_GUSBCFG_IC_TRAFFIC_PULL_REMOVE_OFFSET	27
154 #define DWC2_GUSBCFG_TX_END_DELAY			(1 << 28)
155 #define DWC2_GUSBCFG_TX_END_DELAY_OFFSET		28
156 #define DWC2_GUSBCFG_FORCEHOSTMODE			(1 << 29)
157 #define DWC2_GUSBCFG_FORCEHOSTMODE_OFFSET		29
158 #define DWC2_GUSBCFG_FORCEDEVMODE			(1 << 30)
159 #define DWC2_GUSBCFG_FORCEDEVMODE_OFFSET		30
160 #define DWC2_GLPMCTL_LPM_CAP_EN				(1 << 0)
161 #define DWC2_GLPMCTL_LPM_CAP_EN_OFFSET			0
162 #define DWC2_GLPMCTL_APPL_RESP				(1 << 1)
163 #define DWC2_GLPMCTL_APPL_RESP_OFFSET			1
164 #define DWC2_GLPMCTL_HIRD_MASK				(0xF << 2)
165 #define DWC2_GLPMCTL_HIRD_OFFSET			2
166 #define DWC2_GLPMCTL_REM_WKUP_EN			(1 << 6)
167 #define DWC2_GLPMCTL_REM_WKUP_EN_OFFSET			6
168 #define DWC2_GLPMCTL_EN_UTMI_SLEEP			(1 << 7)
169 #define DWC2_GLPMCTL_EN_UTMI_SLEEP_OFFSET		7
170 #define DWC2_GLPMCTL_HIRD_THRES_MASK			(0x1F << 8)
171 #define DWC2_GLPMCTL_HIRD_THRES_OFFSET			8
172 #define DWC2_GLPMCTL_LPM_RESP_MASK			(0x3 << 13)
173 #define DWC2_GLPMCTL_LPM_RESP_OFFSET			13
174 #define DWC2_GLPMCTL_PRT_SLEEP_STS			(1 << 15)
175 #define DWC2_GLPMCTL_PRT_SLEEP_STS_OFFSET		15
176 #define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK		(1 << 16)
177 #define DWC2_GLPMCTL_SLEEP_STATE_RESUMEOK_OFFSET	16
178 #define DWC2_GLPMCTL_LPM_CHAN_INDEX_MASK		(0xF << 17)
179 #define DWC2_GLPMCTL_LPM_CHAN_INDEX_OFFSET		17
180 #define DWC2_GLPMCTL_RETRY_COUNT_MASK			(0x7 << 21)
181 #define DWC2_GLPMCTL_RETRY_COUNT_OFFSET			21
182 #define DWC2_GLPMCTL_SEND_LPM				(1 << 24)
183 #define DWC2_GLPMCTL_SEND_LPM_OFFSET			24
184 #define DWC2_GLPMCTL_RETRY_COUNT_STS_MASK		(0x7 << 25)
185 #define DWC2_GLPMCTL_RETRY_COUNT_STS_OFFSET		25
186 #define DWC2_GLPMCTL_HSIC_CONNECT			(1 << 30)
187 #define DWC2_GLPMCTL_HSIC_CONNECT_OFFSET		30
188 #define DWC2_GLPMCTL_INV_SEL_HSIC			(1 << 31)
189 #define DWC2_GLPMCTL_INV_SEL_HSIC_OFFSET		31
190 #define DWC2_GRSTCTL_CSFTRST				(1 << 0)
191 #define DWC2_GRSTCTL_CSFTRST_OFFSET			0
192 #define DWC2_GRSTCTL_HSFTRST				(1 << 1)
193 #define DWC2_GRSTCTL_HSFTRST_OFFSET			1
194 #define DWC2_GRSTCTL_HSTFRM				(1 << 2)
195 #define DWC2_GRSTCTL_HSTFRM_OFFSET			2
196 #define DWC2_GRSTCTL_INTKNQFLSH				(1 << 3)
197 #define DWC2_GRSTCTL_INTKNQFLSH_OFFSET			3
198 #define DWC2_GRSTCTL_RXFFLSH				(1 << 4)
199 #define DWC2_GRSTCTL_RXFFLSH_OFFSET			4
200 #define DWC2_GRSTCTL_TXFFLSH				(1 << 5)
201 #define DWC2_GRSTCTL_TXFFLSH_OFFSET			5
202 #define DWC2_GRSTCTL_TXFNUM_MASK			(0x1F << 6)
203 #define DWC2_GRSTCTL_TXFNUM_OFFSET			6
204 #define DWC2_GRSTCTL_DMAREQ				(1 << 30)
205 #define DWC2_GRSTCTL_DMAREQ_OFFSET			30
206 #define DWC2_GRSTCTL_AHBIDLE				(1 << 31)
207 #define DWC2_GRSTCTL_AHBIDLE_OFFSET			31
208 #define DWC2_GINTMSK_MODEMISMATCH			(1 << 1)
209 #define DWC2_GINTMSK_MODEMISMATCH_OFFSET		1
210 #define DWC2_GINTMSK_OTGINTR				(1 << 2)
211 #define DWC2_GINTMSK_OTGINTR_OFFSET			2
212 #define DWC2_GINTMSK_SOFINTR				(1 << 3)
213 #define DWC2_GINTMSK_SOFINTR_OFFSET			3
214 #define DWC2_GINTMSK_RXSTSQLVL				(1 << 4)
215 #define DWC2_GINTMSK_RXSTSQLVL_OFFSET			4
216 #define DWC2_GINTMSK_NPTXFEMPTY				(1 << 5)
217 #define DWC2_GINTMSK_NPTXFEMPTY_OFFSET			5
218 #define DWC2_GINTMSK_GINNAKEFF				(1 << 6)
219 #define DWC2_GINTMSK_GINNAKEFF_OFFSET			6
220 #define DWC2_GINTMSK_GOUTNAKEFF				(1 << 7)
221 #define DWC2_GINTMSK_GOUTNAKEFF_OFFSET			7
222 #define DWC2_GINTMSK_I2CINTR				(1 << 9)
223 #define DWC2_GINTMSK_I2CINTR_OFFSET			9
224 #define DWC2_GINTMSK_ERLYSUSPEND			(1 << 10)
225 #define DWC2_GINTMSK_ERLYSUSPEND_OFFSET			10
226 #define DWC2_GINTMSK_USBSUSPEND				(1 << 11)
227 #define DWC2_GINTMSK_USBSUSPEND_OFFSET			11
228 #define DWC2_GINTMSK_USBRESET				(1 << 12)
229 #define DWC2_GINTMSK_USBRESET_OFFSET			12
230 #define DWC2_GINTMSK_ENUMDONE				(1 << 13)
231 #define DWC2_GINTMSK_ENUMDONE_OFFSET			13
232 #define DWC2_GINTMSK_ISOOUTDROP				(1 << 14)
233 #define DWC2_GINTMSK_ISOOUTDROP_OFFSET			14
234 #define DWC2_GINTMSK_EOPFRAME				(1 << 15)
235 #define DWC2_GINTMSK_EOPFRAME_OFFSET			15
236 #define DWC2_GINTMSK_EPMISMATCH				(1 << 17)
237 #define DWC2_GINTMSK_EPMISMATCH_OFFSET			17
238 #define DWC2_GINTMSK_INEPINTR				(1 << 18)
239 #define DWC2_GINTMSK_INEPINTR_OFFSET			18
240 #define DWC2_GINTMSK_OUTEPINTR				(1 << 19)
241 #define DWC2_GINTMSK_OUTEPINTR_OFFSET			19
242 #define DWC2_GINTMSK_INCOMPLISOIN			(1 << 20)
243 #define DWC2_GINTMSK_INCOMPLISOIN_OFFSET		20
244 #define DWC2_GINTMSK_INCOMPLISOOUT			(1 << 21)
245 #define DWC2_GINTMSK_INCOMPLISOOUT_OFFSET		21
246 #define DWC2_GINTMSK_PORTINTR				(1 << 24)
247 #define DWC2_GINTMSK_PORTINTR_OFFSET			24
248 #define DWC2_GINTMSK_HCINTR				(1 << 25)
249 #define DWC2_GINTMSK_HCINTR_OFFSET			25
250 #define DWC2_GINTMSK_PTXFEMPTY				(1 << 26)
251 #define DWC2_GINTMSK_PTXFEMPTY_OFFSET			26
252 #define DWC2_GINTMSK_LPMTRANRCVD			(1 << 27)
253 #define DWC2_GINTMSK_LPMTRANRCVD_OFFSET			27
254 #define DWC2_GINTMSK_CONIDSTSCHNG			(1 << 28)
255 #define DWC2_GINTMSK_CONIDSTSCHNG_OFFSET		28
256 #define DWC2_GINTMSK_DISCONNECT				(1 << 29)
257 #define DWC2_GINTMSK_DISCONNECT_OFFSET			29
258 #define DWC2_GINTMSK_SESSREQINTR			(1 << 30)
259 #define DWC2_GINTMSK_SESSREQINTR_OFFSET			30
260 #define DWC2_GINTMSK_WKUPINTR				(1 << 31)
261 #define DWC2_GINTMSK_WKUPINTR_OFFSET			31
262 #define DWC2_GINTSTS_CURMODE_DEVICE			(0 << 0)
263 #define DWC2_GINTSTS_CURMODE_HOST			(1 << 0)
264 #define DWC2_GINTSTS_CURMODE				(1 << 0)
265 #define DWC2_GINTSTS_CURMODE_OFFSET			0
266 #define DWC2_GINTSTS_MODEMISMATCH			(1 << 1)
267 #define DWC2_GINTSTS_MODEMISMATCH_OFFSET		1
268 #define DWC2_GINTSTS_OTGINTR				(1 << 2)
269 #define DWC2_GINTSTS_OTGINTR_OFFSET			2
270 #define DWC2_GINTSTS_SOFINTR				(1 << 3)
271 #define DWC2_GINTSTS_SOFINTR_OFFSET			3
272 #define DWC2_GINTSTS_RXSTSQLVL				(1 << 4)
273 #define DWC2_GINTSTS_RXSTSQLVL_OFFSET			4
274 #define DWC2_GINTSTS_NPTXFEMPTY				(1 << 5)
275 #define DWC2_GINTSTS_NPTXFEMPTY_OFFSET			5
276 #define DWC2_GINTSTS_GINNAKEFF				(1 << 6)
277 #define DWC2_GINTSTS_GINNAKEFF_OFFSET			6
278 #define DWC2_GINTSTS_GOUTNAKEFF				(1 << 7)
279 #define DWC2_GINTSTS_GOUTNAKEFF_OFFSET			7
280 #define DWC2_GINTSTS_I2CINTR				(1 << 9)
281 #define DWC2_GINTSTS_I2CINTR_OFFSET			9
282 #define DWC2_GINTSTS_ERLYSUSPEND			(1 << 10)
283 #define DWC2_GINTSTS_ERLYSUSPEND_OFFSET			10
284 #define DWC2_GINTSTS_USBSUSPEND				(1 << 11)
285 #define DWC2_GINTSTS_USBSUSPEND_OFFSET			11
286 #define DWC2_GINTSTS_USBRESET				(1 << 12)
287 #define DWC2_GINTSTS_USBRESET_OFFSET			12
288 #define DWC2_GINTSTS_ENUMDONE				(1 << 13)
289 #define DWC2_GINTSTS_ENUMDONE_OFFSET			13
290 #define DWC2_GINTSTS_ISOOUTDROP				(1 << 14)
291 #define DWC2_GINTSTS_ISOOUTDROP_OFFSET			14
292 #define DWC2_GINTSTS_EOPFRAME				(1 << 15)
293 #define DWC2_GINTSTS_EOPFRAME_OFFSET			15
294 #define DWC2_GINTSTS_INTOKENRX				(1 << 16)
295 #define DWC2_GINTSTS_INTOKENRX_OFFSET			16
296 #define DWC2_GINTSTS_EPMISMATCH				(1 << 17)
297 #define DWC2_GINTSTS_EPMISMATCH_OFFSET			17
298 #define DWC2_GINTSTS_INEPINT				(1 << 18)
299 #define DWC2_GINTSTS_INEPINT_OFFSET			18
300 #define DWC2_GINTSTS_OUTEPINTR				(1 << 19)
301 #define DWC2_GINTSTS_OUTEPINTR_OFFSET			19
302 #define DWC2_GINTSTS_INCOMPLISOIN			(1 << 20)
303 #define DWC2_GINTSTS_INCOMPLISOIN_OFFSET		20
304 #define DWC2_GINTSTS_INCOMPLISOOUT			(1 << 21)
305 #define DWC2_GINTSTS_INCOMPLISOOUT_OFFSET		21
306 #define DWC2_GINTSTS_PORTINTR				(1 << 24)
307 #define DWC2_GINTSTS_PORTINTR_OFFSET			24
308 #define DWC2_GINTSTS_HCINTR				(1 << 25)
309 #define DWC2_GINTSTS_HCINTR_OFFSET			25
310 #define DWC2_GINTSTS_PTXFEMPTY				(1 << 26)
311 #define DWC2_GINTSTS_PTXFEMPTY_OFFSET			26
312 #define DWC2_GINTSTS_LPMTRANRCVD			(1 << 27)
313 #define DWC2_GINTSTS_LPMTRANRCVD_OFFSET			27
314 #define DWC2_GINTSTS_CONIDSTSCHNG			(1 << 28)
315 #define DWC2_GINTSTS_CONIDSTSCHNG_OFFSET		28
316 #define DWC2_GINTSTS_DISCONNECT				(1 << 29)
317 #define DWC2_GINTSTS_DISCONNECT_OFFSET			29
318 #define DWC2_GINTSTS_SESSREQINTR			(1 << 30)
319 #define DWC2_GINTSTS_SESSREQINTR_OFFSET			30
320 #define DWC2_GINTSTS_WKUPINTR				(1 << 31)
321 #define DWC2_GINTSTS_WKUPINTR_OFFSET			31
322 #define DWC2_GRXSTS_EPNUM_MASK				(0xF << 0)
323 #define DWC2_GRXSTS_EPNUM_OFFSET			0
324 #define DWC2_GRXSTS_BCNT_MASK				(0x7FF << 4)
325 #define DWC2_GRXSTS_BCNT_OFFSET				4
326 #define DWC2_GRXSTS_DPID_MASK				(0x3 << 15)
327 #define DWC2_GRXSTS_DPID_OFFSET				15
328 #define DWC2_GRXSTS_PKTSTS_MASK				(0xF << 17)
329 #define DWC2_GRXSTS_PKTSTS_OFFSET			17
330 #define DWC2_GRXSTS_FN_MASK				(0xF << 21)
331 #define DWC2_GRXSTS_FN_OFFSET				21
332 #define DWC2_FIFOSIZE_STARTADDR_MASK			(0xFFFF << 0)
333 #define DWC2_FIFOSIZE_STARTADDR_OFFSET			0
334 #define DWC2_FIFOSIZE_DEPTH_MASK			(0xFFFF << 16)
335 #define DWC2_FIFOSIZE_DEPTH_OFFSET			16
336 #define DWC2_GNPTXSTS_NPTXFSPCAVAIL_MASK		(0xFFFF << 0)
337 #define DWC2_GNPTXSTS_NPTXFSPCAVAIL_OFFSET		0
338 #define DWC2_GNPTXSTS_NPTXQSPCAVAIL_MASK		(0xFF << 16)
339 #define DWC2_GNPTXSTS_NPTXQSPCAVAIL_OFFSET		16
340 #define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE		(1 << 24)
341 #define DWC2_GNPTXSTS_NPTXQTOP_TERMINATE_OFFSET		24
342 #define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_MASK		(0x3 << 25)
343 #define DWC2_GNPTXSTS_NPTXQTOP_TOKEN_OFFSET		25
344 #define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_MASK		(0xF << 27)
345 #define DWC2_GNPTXSTS_NPTXQTOP_CHNEP_OFFSET		27
346 #define DWC2_DTXFSTS_TXFSPCAVAIL_MASK			(0xFFFF << 0)
347 #define DWC2_DTXFSTS_TXFSPCAVAIL_OFFSET			0
348 #define DWC2_GI2CCTL_RWDATA_MASK			(0xFF << 0)
349 #define DWC2_GI2CCTL_RWDATA_OFFSET			0
350 #define DWC2_GI2CCTL_REGADDR_MASK			(0xFF << 8)
351 #define DWC2_GI2CCTL_REGADDR_OFFSET			8
352 #define DWC2_GI2CCTL_ADDR_MASK				(0x7F << 16)
353 #define DWC2_GI2CCTL_ADDR_OFFSET			16
354 #define DWC2_GI2CCTL_I2CEN				(1 << 23)
355 #define DWC2_GI2CCTL_I2CEN_OFFSET			23
356 #define DWC2_GI2CCTL_ACK				(1 << 24)
357 #define DWC2_GI2CCTL_ACK_OFFSET				24
358 #define DWC2_GI2CCTL_I2CSUSPCTL				(1 << 25)
359 #define DWC2_GI2CCTL_I2CSUSPCTL_OFFSET			25
360 #define DWC2_GI2CCTL_I2CDEVADDR_MASK			(0x3 << 26)
361 #define DWC2_GI2CCTL_I2CDEVADDR_OFFSET			26
362 #define DWC2_GI2CCTL_RW					(1 << 30)
363 #define DWC2_GI2CCTL_RW_OFFSET				30
364 #define DWC2_GI2CCTL_BSYDNE				(1 << 31)
365 #define DWC2_GI2CCTL_BSYDNE_OFFSET			31
366 #define DWC2_HWCFG1_EP_DIR0_MASK			(0x3 << 0)
367 #define DWC2_HWCFG1_EP_DIR0_OFFSET			0
368 #define DWC2_HWCFG1_EP_DIR1_MASK			(0x3 << 2)
369 #define DWC2_HWCFG1_EP_DIR1_OFFSET			2
370 #define DWC2_HWCFG1_EP_DIR2_MASK			(0x3 << 4)
371 #define DWC2_HWCFG1_EP_DIR2_OFFSET			4
372 #define DWC2_HWCFG1_EP_DIR3_MASK			(0x3 << 6)
373 #define DWC2_HWCFG1_EP_DIR3_OFFSET			6
374 #define DWC2_HWCFG1_EP_DIR4_MASK			(0x3 << 8)
375 #define DWC2_HWCFG1_EP_DIR4_OFFSET			8
376 #define DWC2_HWCFG1_EP_DIR5_MASK			(0x3 << 10)
377 #define DWC2_HWCFG1_EP_DIR5_OFFSET			10
378 #define DWC2_HWCFG1_EP_DIR6_MASK			(0x3 << 12)
379 #define DWC2_HWCFG1_EP_DIR6_OFFSET			12
380 #define DWC2_HWCFG1_EP_DIR7_MASK			(0x3 << 14)
381 #define DWC2_HWCFG1_EP_DIR7_OFFSET			14
382 #define DWC2_HWCFG1_EP_DIR8_MASK			(0x3 << 16)
383 #define DWC2_HWCFG1_EP_DIR8_OFFSET			16
384 #define DWC2_HWCFG1_EP_DIR9_MASK			(0x3 << 18)
385 #define DWC2_HWCFG1_EP_DIR9_OFFSET			18
386 #define DWC2_HWCFG1_EP_DIR10_MASK			(0x3 << 20)
387 #define DWC2_HWCFG1_EP_DIR10_OFFSET			20
388 #define DWC2_HWCFG1_EP_DIR11_MASK			(0x3 << 22)
389 #define DWC2_HWCFG1_EP_DIR11_OFFSET			22
390 #define DWC2_HWCFG1_EP_DIR12_MASK			(0x3 << 24)
391 #define DWC2_HWCFG1_EP_DIR12_OFFSET			24
392 #define DWC2_HWCFG1_EP_DIR13_MASK			(0x3 << 26)
393 #define DWC2_HWCFG1_EP_DIR13_OFFSET			26
394 #define DWC2_HWCFG1_EP_DIR14_MASK			(0x3 << 28)
395 #define DWC2_HWCFG1_EP_DIR14_OFFSET			28
396 #define DWC2_HWCFG1_EP_DIR15_MASK			(0x3 << 30)
397 #define DWC2_HWCFG1_EP_DIR15_OFFSET			30
398 #define DWC2_HWCFG2_OP_MODE_MASK			(0x7 << 0)
399 #define DWC2_HWCFG2_OP_MODE_OFFSET			0
400 #define DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY		(0x0 << 3)
401 #define DWC2_HWCFG2_ARCHITECTURE_EXT_DMA		(0x1 << 3)
402 #define DWC2_HWCFG2_ARCHITECTURE_INT_DMA		(0x2 << 3)
403 #define DWC2_HWCFG2_ARCHITECTURE_MASK			(0x3 << 3)
404 #define DWC2_HWCFG2_ARCHITECTURE_OFFSET			3
405 #define DWC2_HWCFG2_POINT2POINT				(1 << 5)
406 #define DWC2_HWCFG2_POINT2POINT_OFFSET			5
407 #define DWC2_HWCFG2_HS_PHY_TYPE_MASK			(0x3 << 6)
408 #define DWC2_HWCFG2_HS_PHY_TYPE_OFFSET			6
409 #define DWC2_HWCFG2_FS_PHY_TYPE_MASK			(0x3 << 8)
410 #define DWC2_HWCFG2_FS_PHY_TYPE_OFFSET			8
411 #define DWC2_HWCFG2_NUM_DEV_EP_MASK			(0xF << 10)
412 #define DWC2_HWCFG2_NUM_DEV_EP_OFFSET			10
413 #define DWC2_HWCFG2_NUM_HOST_CHAN_MASK			(0xF << 14)
414 #define DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET		14
415 #define DWC2_HWCFG2_PERIO_EP_SUPPORTED			(1 << 18)
416 #define DWC2_HWCFG2_PERIO_EP_SUPPORTED_OFFSET		18
417 #define DWC2_HWCFG2_DYNAMIC_FIFO			(1 << 19)
418 #define DWC2_HWCFG2_DYNAMIC_FIFO_OFFSET			19
419 #define DWC2_HWCFG2_MULTI_PROC_INT			(1 << 20)
420 #define DWC2_HWCFG2_MULTI_PROC_INT_OFFSET		20
421 #define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_MASK		(0x3 << 22)
422 #define DWC2_HWCFG2_NONPERIO_TX_Q_DEPTH_OFFSET		22
423 #define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK		(0x3 << 24)
424 #define DWC2_HWCFG2_HOST_PERIO_TX_Q_DEPTH_OFFSET	24
425 #define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_MASK		(0x1F << 26)
426 #define DWC2_HWCFG2_DEV_TOKEN_Q_DEPTH_OFFSET		26
427 #define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_MASK		(0xF << 0)
428 #define DWC2_HWCFG3_XFER_SIZE_CNTR_WIDTH_OFFSET		0
429 #define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK		(0x7 << 4)
430 #define DWC2_HWCFG3_PACKET_SIZE_CNTR_WIDTH_OFFSET	4
431 #define DWC2_HWCFG3_OTG_FUNC				(1 << 7)
432 #define DWC2_HWCFG3_OTG_FUNC_OFFSET			7
433 #define DWC2_HWCFG3_I2C					(1 << 8)
434 #define DWC2_HWCFG3_I2C_OFFSET				8
435 #define DWC2_HWCFG3_VENDOR_CTRL_IF			(1 << 9)
436 #define DWC2_HWCFG3_VENDOR_CTRL_IF_OFFSET		9
437 #define DWC2_HWCFG3_OPTIONAL_FEATURES			(1 << 10)
438 #define DWC2_HWCFG3_OPTIONAL_FEATURES_OFFSET		10
439 #define DWC2_HWCFG3_SYNCH_RESET_TYPE			(1 << 11)
440 #define DWC2_HWCFG3_SYNCH_RESET_TYPE_OFFSET		11
441 #define DWC2_HWCFG3_OTG_ENABLE_IC_USB			(1 << 12)
442 #define DWC2_HWCFG3_OTG_ENABLE_IC_USB_OFFSET		12
443 #define DWC2_HWCFG3_OTG_ENABLE_HSIC			(1 << 13)
444 #define DWC2_HWCFG3_OTG_ENABLE_HSIC_OFFSET		13
445 #define DWC2_HWCFG3_OTG_LPM_EN				(1 << 15)
446 #define DWC2_HWCFG3_OTG_LPM_EN_OFFSET			15
447 #define DWC2_HWCFG3_DFIFO_DEPTH_MASK			(0xFFFF << 16)
448 #define DWC2_HWCFG3_DFIFO_DEPTH_OFFSET			16
449 #define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_MASK		(0xF << 0)
450 #define DWC2_HWCFG4_NUM_DEV_PERIO_IN_EP_OFFSET		0
451 #define DWC2_HWCFG4_POWER_OPTIMIZ			(1 << 4)
452 #define DWC2_HWCFG4_POWER_OPTIMIZ_OFFSET		4
453 #define DWC2_HWCFG4_MIN_AHB_FREQ_MASK			(0x1FF << 5)
454 #define DWC2_HWCFG4_MIN_AHB_FREQ_OFFSET			5
455 #define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_MASK		(0x3 << 14)
456 #define DWC2_HWCFG4_UTMI_PHY_DATA_WIDTH_OFFSET		14
457 #define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_MASK		(0xF << 16)
458 #define DWC2_HWCFG4_NUM_DEV_MODE_CTRL_EP_OFFSET		16
459 #define DWC2_HWCFG4_IDDIG_FILT_EN			(1 << 20)
460 #define DWC2_HWCFG4_IDDIG_FILT_EN_OFFSET		20
461 #define DWC2_HWCFG4_VBUS_VALID_FILT_EN			(1 << 21)
462 #define DWC2_HWCFG4_VBUS_VALID_FILT_EN_OFFSET		21
463 #define DWC2_HWCFG4_A_VALID_FILT_EN			(1 << 22)
464 #define DWC2_HWCFG4_A_VALID_FILT_EN_OFFSET		22
465 #define DWC2_HWCFG4_B_VALID_FILT_EN			(1 << 23)
466 #define DWC2_HWCFG4_B_VALID_FILT_EN_OFFSET		23
467 #define DWC2_HWCFG4_SESSION_END_FILT_EN			(1 << 24)
468 #define DWC2_HWCFG4_SESSION_END_FILT_EN_OFFSET		24
469 #define DWC2_HWCFG4_DED_FIFO_EN				(1 << 25)
470 #define DWC2_HWCFG4_DED_FIFO_EN_OFFSET			25
471 #define DWC2_HWCFG4_NUM_IN_EPS_MASK			(0xF << 26)
472 #define DWC2_HWCFG4_NUM_IN_EPS_OFFSET			26
473 #define DWC2_HWCFG4_DESC_DMA				(1 << 30)
474 #define DWC2_HWCFG4_DESC_DMA_OFFSET			30
475 #define DWC2_HWCFG4_DESC_DMA_DYN			(1 << 31)
476 #define DWC2_HWCFG4_DESC_DMA_DYN_OFFSET			31
477 #define DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ			0
478 #define DWC2_HCFG_FSLSPCLKSEL_48_MHZ			1
479 #define DWC2_HCFG_FSLSPCLKSEL_6_MHZ			2
480 #define DWC2_HCFG_FSLSPCLKSEL_MASK			(0x3 << 0)
481 #define DWC2_HCFG_FSLSPCLKSEL_OFFSET			0
482 #define DWC2_HCFG_FSLSSUPP				(1 << 2)
483 #define DWC2_HCFG_FSLSSUPP_OFFSET			2
484 #define DWC2_HCFG_DESCDMA				(1 << 23)
485 #define DWC2_HCFG_DESCDMA_OFFSET			23
486 #define DWC2_HCFG_FRLISTEN_MASK				(0x3 << 24)
487 #define DWC2_HCFG_FRLISTEN_OFFSET			24
488 #define DWC2_HCFG_PERSCHEDENA				(1 << 26)
489 #define DWC2_HCFG_PERSCHEDENA_OFFSET			26
490 #define DWC2_HCFG_PERSCHEDSTAT				(1 << 27)
491 #define DWC2_HCFG_PERSCHEDSTAT_OFFSET			27
492 #define DWC2_HFIR_FRINT_MASK				(0xFFFF << 0)
493 #define DWC2_HFIR_FRINT_OFFSET				0
494 #define DWC2_HFNUM_FRNUM_MASK				(0xFFFF << 0)
495 #define DWC2_HFNUM_FRNUM_OFFSET				0
496 #define DWC2_HFNUM_FRREM_MASK				(0xFFFF << 16)
497 #define DWC2_HFNUM_FRREM_OFFSET				16
498 #define DWC2_HPTXSTS_PTXFSPCAVAIL_MASK			(0xFFFF << 0)
499 #define DWC2_HPTXSTS_PTXFSPCAVAIL_OFFSET		0
500 #define DWC2_HPTXSTS_PTXQSPCAVAIL_MASK			(0xFF << 16)
501 #define DWC2_HPTXSTS_PTXQSPCAVAIL_OFFSET		16
502 #define DWC2_HPTXSTS_PTXQTOP_TERMINATE			(1 << 24)
503 #define DWC2_HPTXSTS_PTXQTOP_TERMINATE_OFFSET		24
504 #define DWC2_HPTXSTS_PTXQTOP_TOKEN_MASK			(0x3 << 25)
505 #define DWC2_HPTXSTS_PTXQTOP_TOKEN_OFFSET		25
506 #define DWC2_HPTXSTS_PTXQTOP_CHNUM_MASK			(0xF << 27)
507 #define DWC2_HPTXSTS_PTXQTOP_CHNUM_OFFSET		27
508 #define DWC2_HPTXSTS_PTXQTOP_ODD			(1 << 31)
509 #define DWC2_HPTXSTS_PTXQTOP_ODD_OFFSET			31
510 #define DWC2_HPRT0_PRTCONNSTS				(1 << 0)
511 #define DWC2_HPRT0_PRTCONNSTS_OFFSET			0
512 #define DWC2_HPRT0_PRTCONNDET				(1 << 1)
513 #define DWC2_HPRT0_PRTCONNDET_OFFSET			1
514 #define DWC2_HPRT0_PRTENA				(1 << 2)
515 #define DWC2_HPRT0_PRTENA_OFFSET			2
516 #define DWC2_HPRT0_PRTENCHNG				(1 << 3)
517 #define DWC2_HPRT0_PRTENCHNG_OFFSET			3
518 #define DWC2_HPRT0_PRTOVRCURRACT			(1 << 4)
519 #define DWC2_HPRT0_PRTOVRCURRACT_OFFSET			4
520 #define DWC2_HPRT0_PRTOVRCURRCHNG			(1 << 5)
521 #define DWC2_HPRT0_PRTOVRCURRCHNG_OFFSET		5
522 #define DWC2_HPRT0_PRTRES				(1 << 6)
523 #define DWC2_HPRT0_PRTRES_OFFSET			6
524 #define DWC2_HPRT0_PRTSUSP				(1 << 7)
525 #define DWC2_HPRT0_PRTSUSP_OFFSET			7
526 #define DWC2_HPRT0_PRTRST				(1 << 8)
527 #define DWC2_HPRT0_PRTRST_OFFSET			8
528 #define DWC2_HPRT0_PRTLNSTS_MASK			(0x3 << 10)
529 #define DWC2_HPRT0_PRTLNSTS_OFFSET			10
530 #define DWC2_HPRT0_PRTPWR				(1 << 12)
531 #define DWC2_HPRT0_PRTPWR_OFFSET			12
532 #define DWC2_HPRT0_PRTTSTCTL_MASK			(0xF << 13)
533 #define DWC2_HPRT0_PRTTSTCTL_OFFSET			13
534 #define DWC2_HPRT0_PRTSPD_MASK				(0x3 << 17)
535 #define DWC2_HPRT0_PRTSPD_OFFSET			17
536 #define DWC2_HAINT_CH0					(1 << 0)
537 #define DWC2_HAINT_CH0_OFFSET				0
538 #define DWC2_HAINT_CH1					(1 << 1)
539 #define DWC2_HAINT_CH1_OFFSET				1
540 #define DWC2_HAINT_CH2					(1 << 2)
541 #define DWC2_HAINT_CH2_OFFSET				2
542 #define DWC2_HAINT_CH3					(1 << 3)
543 #define DWC2_HAINT_CH3_OFFSET				3
544 #define DWC2_HAINT_CH4					(1 << 4)
545 #define DWC2_HAINT_CH4_OFFSET				4
546 #define DWC2_HAINT_CH5					(1 << 5)
547 #define DWC2_HAINT_CH5_OFFSET				5
548 #define DWC2_HAINT_CH6					(1 << 6)
549 #define DWC2_HAINT_CH6_OFFSET				6
550 #define DWC2_HAINT_CH7					(1 << 7)
551 #define DWC2_HAINT_CH7_OFFSET				7
552 #define DWC2_HAINT_CH8					(1 << 8)
553 #define DWC2_HAINT_CH8_OFFSET				8
554 #define DWC2_HAINT_CH9					(1 << 9)
555 #define DWC2_HAINT_CH9_OFFSET				9
556 #define DWC2_HAINT_CH10					(1 << 10)
557 #define DWC2_HAINT_CH10_OFFSET				10
558 #define DWC2_HAINT_CH11					(1 << 11)
559 #define DWC2_HAINT_CH11_OFFSET				11
560 #define DWC2_HAINT_CH12					(1 << 12)
561 #define DWC2_HAINT_CH12_OFFSET				12
562 #define DWC2_HAINT_CH13					(1 << 13)
563 #define DWC2_HAINT_CH13_OFFSET				13
564 #define DWC2_HAINT_CH14					(1 << 14)
565 #define DWC2_HAINT_CH14_OFFSET				14
566 #define DWC2_HAINT_CH15					(1 << 15)
567 #define DWC2_HAINT_CH15_OFFSET				15
568 #define DWC2_HAINT_CHINT_MASK				0xffff
569 #define DWC2_HAINT_CHINT_OFFSET				0
570 #define DWC2_HAINTMSK_CH0				(1 << 0)
571 #define DWC2_HAINTMSK_CH0_OFFSET			0
572 #define DWC2_HAINTMSK_CH1				(1 << 1)
573 #define DWC2_HAINTMSK_CH1_OFFSET			1
574 #define DWC2_HAINTMSK_CH2				(1 << 2)
575 #define DWC2_HAINTMSK_CH2_OFFSET			2
576 #define DWC2_HAINTMSK_CH3				(1 << 3)
577 #define DWC2_HAINTMSK_CH3_OFFSET			3
578 #define DWC2_HAINTMSK_CH4				(1 << 4)
579 #define DWC2_HAINTMSK_CH4_OFFSET			4
580 #define DWC2_HAINTMSK_CH5				(1 << 5)
581 #define DWC2_HAINTMSK_CH5_OFFSET			5
582 #define DWC2_HAINTMSK_CH6				(1 << 6)
583 #define DWC2_HAINTMSK_CH6_OFFSET			6
584 #define DWC2_HAINTMSK_CH7				(1 << 7)
585 #define DWC2_HAINTMSK_CH7_OFFSET			7
586 #define DWC2_HAINTMSK_CH8				(1 << 8)
587 #define DWC2_HAINTMSK_CH8_OFFSET			8
588 #define DWC2_HAINTMSK_CH9				(1 << 9)
589 #define DWC2_HAINTMSK_CH9_OFFSET			9
590 #define DWC2_HAINTMSK_CH10				(1 << 10)
591 #define DWC2_HAINTMSK_CH10_OFFSET			10
592 #define DWC2_HAINTMSK_CH11				(1 << 11)
593 #define DWC2_HAINTMSK_CH11_OFFSET			11
594 #define DWC2_HAINTMSK_CH12				(1 << 12)
595 #define DWC2_HAINTMSK_CH12_OFFSET			12
596 #define DWC2_HAINTMSK_CH13				(1 << 13)
597 #define DWC2_HAINTMSK_CH13_OFFSET			13
598 #define DWC2_HAINTMSK_CH14				(1 << 14)
599 #define DWC2_HAINTMSK_CH14_OFFSET			14
600 #define DWC2_HAINTMSK_CH15				(1 << 15)
601 #define DWC2_HAINTMSK_CH15_OFFSET			15
602 #define DWC2_HAINTMSK_CHINT_MASK			0xffff
603 #define DWC2_HAINTMSK_CHINT_OFFSET			0
604 #define DWC2_HCCHAR_MPS_MASK				(0x7FF << 0)
605 #define DWC2_HCCHAR_MPS_OFFSET				0
606 #define DWC2_HCCHAR_EPNUM_MASK				(0xF << 11)
607 #define DWC2_HCCHAR_EPNUM_OFFSET			11
608 #define DWC2_HCCHAR_EPDIR				(1 << 15)
609 #define DWC2_HCCHAR_EPDIR_OFFSET			15
610 #define DWC2_HCCHAR_LSPDDEV				(1 << 17)
611 #define DWC2_HCCHAR_LSPDDEV_OFFSET			17
612 #define DWC2_HCCHAR_EPTYPE_CONTROL			0
613 #define DWC2_HCCHAR_EPTYPE_ISOC				1
614 #define DWC2_HCCHAR_EPTYPE_BULK				2
615 #define DWC2_HCCHAR_EPTYPE_INTR				3
616 #define DWC2_HCCHAR_EPTYPE_MASK				(0x3 << 18)
617 #define DWC2_HCCHAR_EPTYPE_OFFSET			18
618 #define DWC2_HCCHAR_MULTICNT_MASK			(0x3 << 20)
619 #define DWC2_HCCHAR_MULTICNT_OFFSET			20
620 #define DWC2_HCCHAR_DEVADDR_MASK			(0x7F << 22)
621 #define DWC2_HCCHAR_DEVADDR_OFFSET			22
622 #define DWC2_HCCHAR_ODDFRM				(1 << 29)
623 #define DWC2_HCCHAR_ODDFRM_OFFSET			29
624 #define DWC2_HCCHAR_CHDIS				(1 << 30)
625 #define DWC2_HCCHAR_CHDIS_OFFSET			30
626 #define DWC2_HCCHAR_CHEN				(1 << 31)
627 #define DWC2_HCCHAR_CHEN_OFFSET				31
628 #define DWC2_HCSPLT_PRTADDR_MASK			(0x7F << 0)
629 #define DWC2_HCSPLT_PRTADDR_OFFSET			0
630 #define DWC2_HCSPLT_HUBADDR_MASK			(0x7F << 7)
631 #define DWC2_HCSPLT_HUBADDR_OFFSET			7
632 #define DWC2_HCSPLT_XACTPOS_MASK			(0x3 << 14)
633 #define DWC2_HCSPLT_XACTPOS_OFFSET			14
634 #define DWC2_HCSPLT_COMPSPLT				(1 << 16)
635 #define DWC2_HCSPLT_COMPSPLT_OFFSET			16
636 #define DWC2_HCSPLT_SPLTENA				(1 << 31)
637 #define DWC2_HCSPLT_SPLTENA_OFFSET			31
638 #define DWC2_HCINT_XFERCOMP				(1 << 0)
639 #define DWC2_HCINT_XFERCOMP_OFFSET			0
640 #define DWC2_HCINT_CHHLTD				(1 << 1)
641 #define DWC2_HCINT_CHHLTD_OFFSET			1
642 #define DWC2_HCINT_AHBERR				(1 << 2)
643 #define DWC2_HCINT_AHBERR_OFFSET			2
644 #define DWC2_HCINT_STALL				(1 << 3)
645 #define DWC2_HCINT_STALL_OFFSET				3
646 #define DWC2_HCINT_NAK					(1 << 4)
647 #define DWC2_HCINT_NAK_OFFSET				4
648 #define DWC2_HCINT_ACK					(1 << 5)
649 #define DWC2_HCINT_ACK_OFFSET				5
650 #define DWC2_HCINT_NYET					(1 << 6)
651 #define DWC2_HCINT_NYET_OFFSET				6
652 #define DWC2_HCINT_XACTERR				(1 << 7)
653 #define DWC2_HCINT_XACTERR_OFFSET			7
654 #define DWC2_HCINT_BBLERR				(1 << 8)
655 #define DWC2_HCINT_BBLERR_OFFSET			8
656 #define DWC2_HCINT_FRMOVRUN				(1 << 9)
657 #define DWC2_HCINT_FRMOVRUN_OFFSET			9
658 #define DWC2_HCINT_DATATGLERR				(1 << 10)
659 #define DWC2_HCINT_DATATGLERR_OFFSET			10
660 #define DWC2_HCINT_BNA					(1 << 11)
661 #define DWC2_HCINT_BNA_OFFSET				11
662 #define DWC2_HCINT_XCS_XACT				(1 << 12)
663 #define DWC2_HCINT_XCS_XACT_OFFSET			12
664 #define DWC2_HCINT_FRM_LIST_ROLL			(1 << 13)
665 #define DWC2_HCINT_FRM_LIST_ROLL_OFFSET			13
666 #define DWC2_HCINTMSK_XFERCOMPL				(1 << 0)
667 #define DWC2_HCINTMSK_XFERCOMPL_OFFSET			0
668 #define DWC2_HCINTMSK_CHHLTD				(1 << 1)
669 #define DWC2_HCINTMSK_CHHLTD_OFFSET			1
670 #define DWC2_HCINTMSK_AHBERR				(1 << 2)
671 #define DWC2_HCINTMSK_AHBERR_OFFSET			2
672 #define DWC2_HCINTMSK_STALL				(1 << 3)
673 #define DWC2_HCINTMSK_STALL_OFFSET			3
674 #define DWC2_HCINTMSK_NAK				(1 << 4)
675 #define DWC2_HCINTMSK_NAK_OFFSET			4
676 #define DWC2_HCINTMSK_ACK				(1 << 5)
677 #define DWC2_HCINTMSK_ACK_OFFSET			5
678 #define DWC2_HCINTMSK_NYET				(1 << 6)
679 #define DWC2_HCINTMSK_NYET_OFFSET			6
680 #define DWC2_HCINTMSK_XACTERR				(1 << 7)
681 #define DWC2_HCINTMSK_XACTERR_OFFSET			7
682 #define DWC2_HCINTMSK_BBLERR				(1 << 8)
683 #define DWC2_HCINTMSK_BBLERR_OFFSET			8
684 #define DWC2_HCINTMSK_FRMOVRUN				(1 << 9)
685 #define DWC2_HCINTMSK_FRMOVRUN_OFFSET			9
686 #define DWC2_HCINTMSK_DATATGLERR			(1 << 10)
687 #define DWC2_HCINTMSK_DATATGLERR_OFFSET			10
688 #define DWC2_HCINTMSK_BNA				(1 << 11)
689 #define DWC2_HCINTMSK_BNA_OFFSET			11
690 #define DWC2_HCINTMSK_XCS_XACT				(1 << 12)
691 #define DWC2_HCINTMSK_XCS_XACT_OFFSET			12
692 #define DWC2_HCINTMSK_FRM_LIST_ROLL			(1 << 13)
693 #define DWC2_HCINTMSK_FRM_LIST_ROLL_OFFSET		13
694 #define DWC2_HCTSIZ_XFERSIZE_MASK			0x7ffff
695 #define DWC2_HCTSIZ_XFERSIZE_OFFSET			0
696 #define DWC2_HCTSIZ_SCHINFO_MASK			0xff
697 #define DWC2_HCTSIZ_SCHINFO_OFFSET			0
698 #define DWC2_HCTSIZ_NTD_MASK				(0xff << 8)
699 #define DWC2_HCTSIZ_NTD_OFFSET				8
700 #define DWC2_HCTSIZ_PKTCNT_MASK				(0x3ff << 19)
701 #define DWC2_HCTSIZ_PKTCNT_OFFSET			19
702 #define DWC2_HCTSIZ_PID_MASK				(0x3 << 29)
703 #define DWC2_HCTSIZ_PID_OFFSET				29
704 #define DWC2_HCTSIZ_DOPNG				(1 << 31)
705 #define DWC2_HCTSIZ_DOPNG_OFFSET			31
706 #define DWC2_HCDMA_CTD_MASK				(0xFF << 3)
707 #define DWC2_HCDMA_CTD_OFFSET				3
708 #define DWC2_HCDMA_DMA_ADDR_MASK			(0x1FFFFF << 11)
709 #define DWC2_HCDMA_DMA_ADDR_OFFSET			11
710 #define DWC2_PCGCCTL_STOPPCLK				(1 << 0)
711 #define DWC2_PCGCCTL_STOPPCLK_OFFSET			0
712 #define DWC2_PCGCCTL_GATEHCLK				(1 << 1)
713 #define DWC2_PCGCCTL_GATEHCLK_OFFSET			1
714 #define DWC2_PCGCCTL_PWRCLMP				(1 << 2)
715 #define DWC2_PCGCCTL_PWRCLMP_OFFSET			2
716 #define DWC2_PCGCCTL_RSTPDWNMODULE			(1 << 3)
717 #define DWC2_PCGCCTL_RSTPDWNMODULE_OFFSET		3
718 #define DWC2_PCGCCTL_PHYSUSPENDED			(1 << 4)
719 #define DWC2_PCGCCTL_PHYSUSPENDED_OFFSET		4
720 #define DWC2_PCGCCTL_ENBL_SLEEP_GATING			(1 << 5)
721 #define DWC2_PCGCCTL_ENBL_SLEEP_GATING_OFFSET		5
722 #define DWC2_PCGCCTL_PHY_IN_SLEEP			(1 << 6)
723 #define DWC2_PCGCCTL_PHY_IN_SLEEP_OFFSET		6
724 #define DWC2_PCGCCTL_DEEP_SLEEP				(1 << 7)
725 #define DWC2_PCGCCTL_DEEP_SLEEP_OFFSET			7
726 #define DWC2_SNPSID_DEVID_VER_2xx			(0x4f542 << 12)
727 #define DWC2_SNPSID_DEVID_VER_3xx			(0x4f543 << 12)
728 #define DWC2_SNPSID_DEVID_MASK				(0xfffff << 12)
729 #define DWC2_SNPSID_DEVID_OFFSET			12
730 
731 /* Host controller specific */
732 #define DWC2_HC_PID_DATA0		0
733 #define DWC2_HC_PID_DATA2		1
734 #define DWC2_HC_PID_DATA1		2
735 #define DWC2_HC_PID_MDATA		3
736 #define DWC2_HC_PID_SETUP		3
737 
738 /* roothub.a masks */
739 #define RH_A_NDP	(0xff << 0)	/* number of downstream ports */
740 #define RH_A_PSM	(1 << 8)	/* power switching mode */
741 #define RH_A_NPS	(1 << 9)	/* no power switching */
742 #define RH_A_DT		(1 << 10)	/* device type (mbz) */
743 #define RH_A_OCPM	(1 << 11)	/* over current protection mode */
744 #define RH_A_NOCP	(1 << 12)	/* no over current protection */
745 #define RH_A_POTPGT	(0xff << 24)	/* power on to power good time */
746 
747 /* roothub.b masks */
748 #define RH_B_DR		0x0000ffff	/* device removable flags */
749 #define RH_B_PPCM	0xffff0000	/* port power control mask */
750 
751 #define DWC2_PHY_TYPE_FS		0
752 #define DWC2_PHY_TYPE_UTMI		1
753 #define DWC2_PHY_TYPE_ULPI		2
754 #define CONFIG_DWC2_PHY_TYPE		DWC2_PHY_TYPE_UTMI	/* PHY type */
755 #define CONFIG_DWC2_UTMI_WIDTH		8	/* UTMI bus width (8/16) */
756 
757 #define DWC2_DMA_BURST_SIZE              32      /* DMA burst len */
758 #define DWC2_MAX_CHANNELS                16      /* Max # of EPs */
759 #define DWC2_HOST_RX_FIFO_SIZE           (516 + DWC2_MAX_CHANNELS)
760 #define DWC2_HOST_NPERIO_TX_FIFO_SIZE    0x100   /* nPeriodic TX FIFO */
761 #define DWC2_HOST_PERIO_TX_FIFO_SIZE     0x200   /* Periodic TX FIFO */
762 #define DWC2_MAX_TRANSFER_SIZE           65535
763 #define DWC2_MAX_PACKET_COUNT            511
764 
765 #define DWC2_HC_CHANNEL                 0
766 
767 #define DWC2_STATUS_BUF_SIZE            64
768 #define DWC2_DATA_BUF_SIZE              (64 * 1024)
769 
770 
771 #define USB_PORT_FEAT_CONNECTION     0
772 #define USB_PORT_FEAT_ENABLE         1
773 #define USB_PORT_FEAT_SUSPEND        2
774 #define USB_PORT_FEAT_OVER_CURRENT   3
775 #define USB_PORT_FEAT_RESET          4
776 #define USB_PORT_FEAT_POWER          8
777 #define USB_PORT_FEAT_LOWSPEED       9
778 #define USB_PORT_FEAT_HIGHSPEED      10
779 #define USB_PORT_FEAT_C_CONNECTION   16
780 #define USB_PORT_FEAT_C_ENABLE       17
781 #define USB_PORT_FEAT_C_SUSPEND      18
782 #define USB_PORT_FEAT_C_OVER_CURRENT 19
783 #define USB_PORT_FEAT_C_RESET        20
784 #define USB_PORT_FEAT_TEST           21
785 
786 #endif	/* __DWCHW_H__ */
787