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Searched refs:ISER (Results 1 – 7 of 7) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm0.h311 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register … member
546 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_EnableIRQ()
Dcore_cm0plus.h322 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register … member
657 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_EnableIRQ()
Dcore_sc000.h317 …__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register … member
677 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_EnableIRQ()
Dcore_cm3.h318 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register … member
1345 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ in NVIC_EnableIRQ()
Dcore_sc300.h318 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register … member
1325 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ in NVIC_EnableIRQ()
Dcore_cm4.h365 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register … member
1497 …NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_… in NVIC_EnableIRQ()
Dcore_cm7.h380 …__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register … member
1684 …NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_… in NVIC_EnableIRQ()