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Searched refs:ISPR (Results 1 – 7 of 7) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm0.h315 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register … member
574 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); in NVIC_GetPendingIRQ()
586 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_SetPendingIRQ()
Dcore_cm0plus.h326 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register … member
685 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); in NVIC_GetPendingIRQ()
697 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_SetPendingIRQ()
Dcore_sc000.h321 …__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register … member
705 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); in NVIC_GetPendingIRQ()
717 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); in NVIC_SetPendingIRQ()
Dcore_cm3.h322 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register … member
1373 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1385 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()
Dcore_sc300.h322 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register … member
1353 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1365 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()
Dcore_cm4.h369 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register … member
1525 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1537 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()
Dcore_cm7.h384 …__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register … member
1712 …return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /… in NVIC_GetPendingIRQ()
1724 …NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ in NVIC_SetPendingIRQ()