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Searched refs:MCR (Results 1 – 6 of 6) sorted by relevance

/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/
DPchAccess.h480 UINTN MCR; variable
492 …MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_D…
495 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \
498 …MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_…
499 …dthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1, (VOID *) (UINTN) &MCR); \
514 …MCR = (UINTN) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_D…
517 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) MCR); \
520 …MCR = (UINTN) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_…
521 …idthUint32, (UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR),1,(VOID *) (UINTN) &MCR); \
/device/linaro/bootloader/edk2/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/
DPciHostBridge.asi116 MCR, 32, // Message Control Register
128 Store(Local0, MCR)
141 Store(Local0, MCR)
/device/linaro/bootloader/edk2/MdePkg/Library/BaseCpuLib/Arm/
DCpuFlushTlb.asm34 MCR p15,0,r0,c8,c5,0 ;Invalidate all the unlocked entried in TLB
DCpuSleep.S7 # MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
DCpuSleep.asm7 ; MCR p15,0,r0,c7,c0,4 ;Wait for Interrupt instruction
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/
DHOST_BUS.ASL51 // Initiate regsiter read message on VLV Message Bus MCR