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Searched refs:PCI_CACHELINE_SIZE_OFFSET (Results 1 – 5 of 5) sorted by relevance

/device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/
DPciHostBridgeSupport.c97 PciAddress.Register = PCI_CACHELINE_SIZE_OFFSET; in ChipsetPreprocessController()
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/
DPciDevice.c485 PCI_CACHELINE_SIZE_OFFSET, in PciBusEvent()
/device/linaro/bootloader/edk2/BaseTools/Source/C/Include/IndustryStandard/
Dpci22.h297 #define PCI_CACHELINE_SIZE_OFFSET 0x0C macro
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/
Dpci22.h309 #define PCI_CACHELINE_SIZE_OFFSET 0x0C macro
/device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
DPci22.h532 #define PCI_CACHELINE_SIZE_OFFSET 0x0C macro