1 /** @file 2 Define the PPI to abstract the functions that enable IDE and SATA channels, and to retrieve 3 the base I/O port address for each of the enabled IDE and SATA channels. 4 5 Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> 6 7 This program and the accompanying materials 8 are licensed and made available under the terms and conditions 9 of the BSD License which accompanies this distribution. The 10 full text of the license may be found at 11 http://opensource.org/licenses/bsd-license.php 12 13 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 14 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 15 16 **/ 17 18 #ifndef _PEI_ATA_CONTROLLER_PPI_H_ 19 #define _PEI_ATA_CONTROLLER_PPI_H_ 20 21 /// 22 /// Global ID for the PEI_ATA_CONTROLLER_PPI. 23 /// 24 #define PEI_ATA_CONTROLLER_PPI_GUID \ 25 { \ 26 0xa45e60d1, 0xc719, 0x44aa, {0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d } \ 27 } 28 29 /// 30 /// Forward declaration for the PEI_ATA_CONTROLLER_PPI. 31 /// 32 typedef struct _PEI_ATA_CONTROLLER_PPI PEI_ATA_CONTROLLER_PPI; 33 34 /// 35 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to 36 /// disable the IDE channels. 37 /// This is designed for old generation chipset with PATA/SATA controllers. 38 /// It may be ignored in PPI implementation for new generation chipset without PATA controller. 39 /// 40 #define PEI_ICH_IDE_NONE 0x00 41 42 /// 43 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to 44 /// enable the Primary IDE channel. 45 /// This is designed for old generation chipset with PATA/SATA controllers. 46 /// It may be ignored in PPI implementation for new generation chipset without PATA controller. 47 /// 48 #define PEI_ICH_IDE_PRIMARY 0x01 49 50 /// 51 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to 52 /// enable the Secondary IDE channel. 53 /// This is designed for old generation chipset with PATA/SATA controllers. 54 /// It may be ignored in PPI implementation for new generation chipset without PATA controller. 55 /// 56 #define PEI_ICH_IDE_SECONDARY 0x02 57 58 /// 59 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to 60 /// disable the SATA channel. 61 /// This is designed for old generation chipset with PATA/SATA controllers. 62 /// It may be ignored in PPI implementation for new generation chipset without PATA controller. 63 /// 64 #define PEI_ICH_SATA_NONE 0x04 65 66 /// 67 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to 68 /// enable the Primary SATA channel. 69 /// This is designed for old generation chipset with PATA/SATA controllers. 70 /// It may be ignored in PPI implementation for new generation chipset without PATA controller. 71 /// 72 #define PEI_ICH_SATA_PRIMARY 0x08 73 74 /// 75 /// This bit is used in the ChannelMask parameter of EnableAtaChannel() to 76 /// enable the Secondary SATA channel. 77 /// This is designed for old generation chipset with PATA/SATA controllers. 78 /// It may be ignored in PPI implementation for new generation chipset without PATA controller. 79 /// 80 #define PEI_ICH_SATA_SECONDARY 0x010 81 82 /// 83 /// Structure that contains the base addresses for the IDE registers 84 /// 85 typedef struct { 86 /// 87 /// Base I/O port address of the IDE controller's command block 88 /// 89 UINT16 CommandBlockBaseAddr; 90 /// 91 /// Base I/O port address of the IDE controller's control block 92 /// 93 UINT16 ControlBlockBaseAddr; 94 } IDE_REGS_BASE_ADDR; 95 96 /** 97 Sets IDE and SATA channels to an enabled or disabled state. 98 99 This service enables or disables the IDE and SATA channels specified by ChannelMask. 100 It may ignore ChannelMask setting to enable or disable IDE and SATA channels based on the platform policy. 101 The number of the enabled channels will be returned by GET_IDE_REGS_BASE_ADDR() function. 102 103 If the new state is set, then EFI_SUCCESS is returned. If the new state can 104 not be set, then EFI_DEVICE_ERROR is returned. 105 106 @param[in] PeiServices The pointer to the PEI Services Table. 107 @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI. 108 @param[in] ChannelMask The bitmask that identifies the IDE and SATA channels to 109 enable or disable. This paramter is optional. 110 111 @retval EFI_SUCCESS The IDE or SATA channels were enabled or disabled successfully. 112 @retval EFI_DEVICE_ERROR The IDE or SATA channels could not be enabled or disabled. 113 114 **/ 115 typedef 116 EFI_STATUS 117 (EFIAPI *PEI_ENABLE_ATA)( 118 IN EFI_PEI_SERVICES **PeiServices, 119 IN PEI_ATA_CONTROLLER_PPI *This, 120 IN UINT8 ChannelMask 121 ); 122 123 /** 124 Retrieves the I/O port base addresses for command and control registers of the 125 enabled IDE/SATA channels. 126 127 This service fills in the structure poionted to by IdeRegsBaseAddr with the I/O 128 port base addresses for the command and control registers of the IDE and SATA 129 channels that were previously enabled in EnableAtaChannel(). The number of 130 enabled IDE and SATA channels is returned. 131 132 @param[in] PeiServices The pointer to the PEI Services Table. 133 @param[in] This The pointer to this instance of the PEI_ATA_CONTROLLER_PPI. 134 @param[out] IdeRegsBaseAddr The pointer to caller allocated space to return the 135 I/O port base addresses of the IDE and SATA channels 136 that were previosuly enabled with EnableAtaChannel(). 137 138 @return The number of enabled IDE and SATA channels in the platform. 139 140 **/ 141 typedef 142 UINT32 143 (EFIAPI *GET_IDE_REGS_BASE_ADDR)( 144 IN EFI_PEI_SERVICES **PeiServices, 145 IN PEI_ATA_CONTROLLER_PPI *This, 146 OUT IDE_REGS_BASE_ADDR *IdeRegsBaseAddr 147 ); 148 149 /// 150 /// This PPI contains services to enable and disable IDE and SATA channels and 151 /// retrieves the base I/O port addresses to the enabled IDE and SATA channels. 152 /// 153 struct _PEI_ATA_CONTROLLER_PPI { 154 PEI_ENABLE_ATA EnableAtaChannel; 155 GET_IDE_REGS_BASE_ADDR GetIdeRegsBaseAddr; 156 }; 157 158 extern EFI_GUID gPeiAtaControllerPpiGuid; 159 160 #endif 161 162 163