1 // ++ 2 3 // TODO: fix comment to start with /*++ 4 // 5 // Copyright (c) 2004, Intel Corporation. All rights reserved.<BR> 6 // This program and the accompanying materials 7 // are licensed and made available under the terms and conditions of the BSD License 8 // which accompanies this distribution. The full text of the license may be found at 9 // http://opensource.org/licenses/bsd-license.php 10 // 11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 // 14 // Module Name: 15 // 16 // IpfDefines.h 17 // 18 // Abstract: 19 // 20 // IPF Processor Defines. 21 // NOTE: This file is included by assembly files as well. 22 // 23 // -- 24 // 25 #ifndef _IPFDEFINES_H 26 #define _IPFDEFINES_H 27 28 // 29 // IPI DElivery Methods 30 // 31 #define IPI_INT_DELIVERY 0x0 32 #define IPI_PMI_DELIVERY 0x2 33 #define IPI_NMI_DELIVERY 0x4 34 #define IPI_INIT_DELIVERY 0x5 35 #define IPI_ExtINT_DELIVERY 0x7 36 37 // 38 // Define Itanium-based system registers. 39 // 40 // Define Itanium-based system register bit field offsets. 41 // 42 // Processor Status Register (PSR) Bit positions 43 // 44 // User / System mask 45 // 46 #define PSR_RV0 0 47 #define PSR_BE 1 48 #define PSR_UP 2 49 #define PSR_AC 3 50 #define PSR_MFL 4 51 #define PSR_MFH 5 52 53 // 54 // PSR bits 6-12 reserved (must be zero) 55 // 56 #define PSR_MBZ0 6 57 #define PSR_MBZ0_V 0x1ffUL L 58 59 // 60 // System only mask 61 // 62 #define PSR_IC 13 63 #define PSR_IC_MASK (1 << 13) 64 #define PSR_I 14 65 #define PSR_PK 15 66 #define PSR_MBZ1 16 67 #define PSR_MBZ1_V 0x1UL L 68 #define PSR_DT 17 69 #define PSR_DFL 18 70 #define PSR_DFH 19 71 #define PSR_SP 20 72 #define PSR_PP 21 73 #define PSR_DI 22 74 #define PSR_SI 23 75 #define PSR_DB 24 76 #define PSR_LP 25 77 #define PSR_TB 26 78 #define PSR_RT 27 79 80 // 81 // PSR bits 28-31 reserved (must be zero) 82 // 83 #define PSR_MBZ2 28 84 #define PSR_MBZ2_V 0xfUL L 85 86 // 87 // Neither mask 88 // 89 #define PSR_CPL 32 90 #define PSR_CPL_LEN 2 91 #define PSR_IS 34 92 #define PSR_MC 35 93 #define PSR_IT 36 94 #define PSR_IT_MASK 0x1000000000 95 #define PSR_ID 37 96 #define PSR_DA 38 97 #define PSR_DD 39 98 #define PSR_SS 40 99 #define PSR_RI 41 100 #define PSR_RI_LEN 2 101 #define PSR_ED 43 102 #define PSR_BN 44 103 104 // 105 // PSR bits 45-63 reserved (must be zero) 106 // 107 #define PSR_MBZ3 45 108 #define PSR_MBZ3_V 0xfffffUL L 109 110 // 111 // Floating Point Status Register (FPSR) Bit positions 112 // 113 // 114 // Traps 115 // 116 #define FPSR_VD 0 117 #define FPSR_DD 1 118 #define FPSR_ZD 2 119 #define FPSR_OD 3 120 #define FPSR_UD 4 121 #define FPSR_ID 5 122 123 // 124 // Status Field 0 - Controls 125 // 126 #define FPSR0_FTZ0 6 127 #define FPSR0_WRE0 7 128 #define FPSR0_PC0 8 129 #define FPSR0_RC0 10 130 #define FPSR0_TD0 12 131 132 // 133 // Status Field 0 - Flags 134 // 135 #define FPSR0_V0 13 136 #define FPSR0_D0 14 137 #define FPSR0_Z0 15 138 #define FPSR0_O0 16 139 #define FPSR0_U0 17 140 #define FPSR0_I0 18 141 142 // 143 // Status Field 1 - Controls 144 // 145 #define FPSR1_FTZ0 19 146 #define FPSR1_WRE0 20 147 #define FPSR1_PC0 21 148 #define FPSR1_RC0 23 149 #define FPSR1_TD0 25 150 151 // 152 // Status Field 1 - Flags 153 // 154 #define FPSR1_V0 26 155 #define FPSR1_D0 27 156 #define FPSR1_Z0 28 157 #define FPSR1_O0 29 158 #define FPSR1_U0 30 159 #define FPSR1_I0 31 160 161 // 162 // Status Field 2 - Controls 163 // 164 #define FPSR2_FTZ0 32 165 #define FPSR2_WRE0 33 166 #define FPSR2_PC0 34 167 #define FPSR2_RC0 36 168 #define FPSR2_TD0 38 169 170 // 171 // Status Field 2 - Flags 172 // 173 #define FPSR2_V0 39 174 #define FPSR2_D0 40 175 #define FPSR2_Z0 41 176 #define FPSR2_O0 42 177 #define FPSR2_U0 43 178 #define FPSR2_I0 44 179 180 // 181 // Status Field 3 - Controls 182 // 183 #define FPSR3_FTZ0 45 184 #define FPSR3_WRE0 46 185 #define FPSR3_PC0 47 186 #define FPSR3_RC0 49 187 #define FPSR3_TD0 51 188 189 // 190 // Status Field 0 - Flags 191 // 192 #define FPSR3_V0 52 193 #define FPSR3_D0 53 194 #define FPSR3_Z0 54 195 #define FPSR3_O0 55 196 #define FPSR3_U0 56 197 #define FPSR3_I0 57 198 199 // 200 // FPSR bits 58-63 Reserved -- Must be zero 201 // 202 #define FPSR_MBZ0 58 203 #define FPSR_MBZ0_V 0x3fUL L 204 205 // 206 // For setting up FPSR on kernel entry 207 // All traps are disabled. 208 // 209 #define FPSR_FOR_KERNEL 0x3f 210 211 #define FP_REG_SIZE 16 // 16 byte spill size 212 #define HIGHFP_REGS_LENGTH (96 * 16) 213 214 // 215 // Define hardware Task Priority Register (TPR) 216 // 217 // 218 // TPR bit positions 219 // 220 #define TPR_MIC 4 // Bits 0 - 3 ignored 221 #define TPR_MIC_LEN 4 222 #define TPR_MMI 16 // Mask Maskable Interrupt 223 // 224 // Define hardware Interrupt Status Register (ISR) 225 // 226 // 227 // ISR bit positions 228 // 229 #define ISR_CODE 0 230 #define ISR_CODE_LEN 16 231 #define ISR_CODE_MASK 0xFFFF 232 #define ISR_IA_VECTOR 16 233 #define ISR_IA_VECTOR_LEN 8 234 #define ISR_MBZ0 24 235 #define ISR_MBZ0_V 0xff 236 #define ISR_X 32 237 #define ISR_W 33 238 #define ISR_R 34 239 #define ISR_NA 35 240 #define ISR_SP 36 241 #define ISR_RS 37 242 #define ISR_IR 38 243 #define ISR_NI 39 244 #define ISR_MBZ1 40 245 #define ISR_EI 41 246 #define ISR_ED 43 247 #define ISR_MBZ2 44 248 #define ISR_MBZ2_V 0xfffff 249 250 // 251 // ISR codes 252 // 253 // For General exceptions: ISR{3:0} 254 // 255 #define ISR_ILLEGAL_OP 0 // Illegal operation fault 256 #define ISR_PRIV_OP 1 // Privileged operation fault 257 #define ISR_PRIV_REG 2 // Privileged register fauls 258 #define ISR_RESVD_REG 3 // Reserved register/field flt 259 #define ISR_ILLEGAL_ISA 4 // Disabled instruction set transition fault 260 // 261 // Define hardware Default Control Register (DCR) 262 // 263 // 264 // DCR bit positions 265 // 266 #define DCR_PP 0 267 #define DCR_BE 1 268 #define DCR_LC 2 269 #define DCR_MBZ0 4 270 #define DCR_MBZ0_V 0xf 271 #define DCR_DM 8 272 #define DCR_DP 9 273 #define DCR_DK 10 274 #define DCR_DX 11 275 #define DCR_DR 12 276 #define DCR_DA 13 277 #define DCR_DD 14 278 #define DCR_DEFER_ALL 0x7f00 279 #define DCR_MBZ1 2 280 #define DCR_MBZ1_V 0xffffffffffffUL L 281 282 // 283 // Define hardware RSE Configuration Register 284 // 285 // RS Configuration (RSC) bit field positions 286 // 287 #define RSC_MODE 0 288 #define RSC_PL 2 289 #define RSC_BE 4 290 #define RSC_MBZ0 5 291 #define RSC_MBZ0_V 0x3ff 292 #define RSC_LOADRS 16 293 #define RSC_LOADRS_LEN 14 294 #define RSC_MBZ1 30 295 #define RSC_MBZ1_V 0x3ffffffffUL L 296 297 // 298 // RSC modes 299 // 300 #define RSC_MODE_LY (0x0) // Lazy 301 #define RSC_MODE_SI (0x1) // Store intensive 302 #define RSC_MODE_LI (0x2) // Load intensive 303 #define RSC_MODE_EA (0x3) // Eager 304 // 305 // RSC Endian bit values 306 // 307 #define RSC_BE_LITTLE 0 308 #define RSC_BE_BIG 1 309 310 // 311 // Define Interruption Function State (IFS) Register 312 // 313 // IFS bit field positions 314 // 315 #define IFS_IFM 0 316 #define IFS_IFM_LEN 38 317 #define IFS_MBZ0 38 318 #define IFS_MBZ0_V 0x1ffffff 319 #define IFS_V 63 320 #define IFS_V_LEN 1 321 322 // 323 // IFS is valid when IFS_V = IFS_VALID 324 // 325 #define IFS_VALID 1 326 327 // 328 // Define Page Table Address (PTA) 329 // 330 #define PTA_VE 0 331 #define PTA_VF 8 332 #define PTA_SIZE 2 333 #define PTA_SIZE_LEN 6 334 #define PTA_BASE 15 335 336 // 337 // Define Region Register (RR) 338 // 339 // 340 // RR bit field positions 341 // 342 #define RR_VE 0 343 #define RR_MBZ0 1 344 #define RR_PS 2 345 #define RR_PS_LEN 6 346 #define RR_RID 8 347 #define RR_RID_LEN 24 348 #define RR_MBZ1 32 349 350 // 351 // SAL uses region register 0 and RID of 1000 352 // 353 #define SAL_RID 0x1000 354 #define SAL_RR_REG 0x0 355 #define SAL_TR 0x0 356 357 // 358 // Total number of region registers 359 // 360 #define RR_SIZE 8 361 362 // 363 // Define Protection Key Register (PKR) 364 // 365 // PKR bit field positions 366 // 367 #define PKR_V 0 368 #define PKR_WD 1 369 #define PKR_RD 2 370 #define PKR_XD 3 371 #define PKR_MBZ0 4 372 #define PKR_KEY 8 373 #define PKR_KEY_LEN 24 374 #define PKR_MBZ1 32 375 376 #define PKR_VALID (1 << PKR_V) 377 378 // 379 // Number of protection key registers 380 // 381 #define PKRNUM 8 382 383 // 384 // Define Interruption TLB Insertion register (ITIR) 385 // 386 // 387 // Define Translation Insertion Format (TR) 388 // 389 // PTE0 bit field positions 390 // 391 #define PTE0_P 0 392 #define PTE0_MBZ0 1 393 #define PTE0_MA 2 394 #define PTE0_A 5 395 #define PTE0_D 6 396 #define PTE0_PL 7 397 #define PTE0_AR 9 398 #define PTE0_PPN 12 399 #define PTE0_MBZ1 48 400 #define PTE0_ED 52 401 #define PTE0_IGN0 53 402 403 // 404 // ITIR bit field positions 405 // 406 #define ITIR_MBZ0 0 407 #define ITIR_PS 2 408 #define ITIR_PS_LEN 6 409 #define ITIR_KEY 8 410 #define ITIR_KEY_LEN 24 411 #define ITIR_MBZ1 32 412 #define ITIR_MBZ1_LEN 16 413 #define ITIR_PPN 48 414 #define ITIR_PPN_LEN 15 415 #define ITIR_MBZ2 63 416 417 #define ATTR_IPAGE 0x661 // Access Rights = RWX (bits 11-9=011), PL 0(8-7=0) 418 #define ATTR_DEF_BITS 0x661 // Access Rights = RWX (bits 11-9=010), PL 0(8-7=0) 419 // Dirty (bit 6=1), Accessed (bit 5=1), 420 // MA WB (bits 4-2=000), Present (bit 0=1) 421 // 422 // Memory access rights 423 // 424 #define AR_UR_KR 0x0 // user/kernel read 425 #define AR_URX_KRX 0x1 // user/kernel read and execute 426 #define AR_URW_KRW 0x2 // user/kernel read & write 427 #define AR_URWX_KRWX 0x3 // user/kernel read,write&execute 428 #define AR_UR_KRW 0x4 // user read/kernel read,write 429 #define AR_URX_KRWX 0x5 // user read/execute, kernel all 430 #define AR_URWX_KRW 0x6 // user all, kernel read & write 431 #define AR_UX_KRX 0x7 // user execute only, kernel read and execute 432 // 433 // Memory attribute values 434 // 435 // 436 // The next 4 are all cached, non-sequential & speculative, coherent 437 // 438 #define MA_WBU 0x0 // Write back, unordered 439 // 440 // The next 3 are all non-cached, sequential & non-speculative 441 // 442 #define MA_UC 0x4 // Non-coalescing, sequential & non-speculative 443 #define MA_UCE 0x5 // Non-coalescing, sequential, non-speculative 444 // & fetchadd exported 445 // 446 #define MA_WC 0x6 // Non-cached, Coalescing, non-seq., spec. 447 #define MA_NAT 0xf // NaT page 448 // 449 // Definition of the offset of TRAP/INTERRUPT/FAULT handlers from the 450 // base of IVA (Interruption Vector Address) 451 // 452 #define IVT_SIZE 0x8000 453 #define EXTRA_ALIGNMENT 0x1000 454 455 #define OFF_VHPTFLT 0x0000 // VHPT Translation fault 456 #define OFF_ITLBFLT 0x0400 // Instruction TLB fault 457 #define OFF_DTLBFLT 0x0800 // Data TLB fault 458 #define OFF_ALTITLBFLT 0x0C00 // Alternate ITLB fault 459 #define OFF_ALTDTLBFLT 0x1000 // Alternate DTLB fault 460 #define OFF_NESTEDTLBFLT 0x1400 // Nested TLB fault 461 #define OFF_IKEYMISSFLT 0x1800 // Inst Key Miss fault 462 #define OFF_DKEYMISSFLT 0x1C00 // Data Key Miss fault 463 #define OFF_DIRTYBITFLT 0x2000 // Dirty-Bit fault 464 #define OFF_IACCESSBITFLT 0x2400 // Inst Access-Bit fault 465 #define OFF_DACCESSBITFLT 0x2800 // Data Access-Bit fault 466 #define OFF_BREAKFLT 0x2C00 // Break Inst fault 467 #define OFF_EXTINT 0x3000 // External Interrupt 468 // 469 // Offset 0x3400 to 0x0x4C00 are reserved 470 // 471 #define OFF_PAGENOTPFLT 0x5000 // Page Not Present fault 472 #define OFF_KEYPERMFLT 0x5100 // Key Permission fault 473 #define OFF_IACCESSRTFLT 0x5200 // Inst Access-Rights flt 474 #define OFF_DACCESSRTFLT 0x5300 // Data Access-Rights fault 475 #define OFF_GPFLT 0x5400 // General Exception fault 476 #define OFF_FPDISFLT 0x5500 // Disable-FP fault 477 #define OFF_NATFLT 0x5600 // NAT Consumption fault 478 #define OFF_SPECLNFLT 0x5700 // Speculation fault 479 #define OFF_DBGFLT 0x5900 // Debug fault 480 #define OFF_ALIGNFLT 0x5A00 // Unaligned Reference fault 481 #define OFF_LOCKDREFFLT 0x5B00 // Locked Data Reference fault 482 #define OFF_FPFLT 0x5C00 // Floating Point fault 483 #define OFF_FPTRAP 0x5D00 // Floating Point Trap 484 #define OFF_LOPRIVTRAP 0x5E00 // Lower-Privilege Transfer Trap 485 #define OFF_TAKENBRTRAP 0x5F00 // Taken Branch Trap 486 #define OFF_SSTEPTRAP 0x6000 // Single Step Trap 487 // 488 // Offset 0x6100 to 0x6800 are reserved 489 // 490 #define OFF_IA32EXCEPTN 0x6900 // iA32 Exception 491 #define OFF_IA32INTERCEPT 0x6A00 // iA32 Intercept 492 #define OFF_IA32INT 0x6B00 // iA32 Interrupt 493 #define NUMBER_OF_VECTORS 0x100 494 // 495 // Privilege levels 496 // 497 #define PL_KERNEL 0 498 #define PL_USER 3 499 500 // 501 // Instruction set (IS) bits 502 // 503 #define IS_IA64 0 504 #define IS_IA 1 505 506 // 507 // RSC while in kernel: enabled, little endian, PL = 0, eager mode 508 // 509 #define RSC_KERNEL ((RSC_MODE_EA << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE)) 510 511 // 512 // Lazy RSC in kernel: enabled, little endian, pl = 0, lazy mode 513 // 514 #define RSC_KERNEL_LAZ ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE)) 515 516 // 517 // RSE disabled: disabled, PL = 0, little endian, eager mode 518 // 519 #define RSC_KERNEL_DISABLED ((RSC_MODE_LY << RSC_MODE) | (RSC_BE_LITTLE << RSC_BE)) 520 521 #define NAT_BITS_PER_RNAT_REG 63 522 523 // 524 // Macros for generating PTE0 and PTE1 value 525 // 526 #define PTE0(ed, ppn12_47, ar, pl, d, a, ma, p) \ 527 ( ( ed << PTE0_ED ) | \ 528 ( ppn12_47 << PTE0_PPN ) | \ 529 ( ar << PTE0_AR ) | \ 530 ( pl << PTE0_PL ) | \ 531 ( d << PTE0_D ) | \ 532 ( a << PTE0_A ) | \ 533 ( ma << PTE0_MA ) | \ 534 ( p << PTE0_P ) \ 535 ) 536 537 #define ITIR(ppn48_63, key, ps) \ 538 ( ( ps << ITIR_PS ) | \ 539 ( key << ITIR_KEY ) | \ 540 ( ppn48_63 << ITIR_PPN ) \ 541 ) 542 543 // 544 // Macro to generate mask value from bit position. The result is a 545 // 64-bit. 546 // 547 #define BITMASK(bp, value) (value << bp) 548 549 #define BUNDLE_SIZE 16 550 #define SPURIOUS_INT 0xF 551 552 #define FAST_DISABLE_INTERRUPTS rsm BITMASK (PSR_I, 1);; 553 554 #define FAST_ENABLE_INTERRUPTS ssm BITMASK (PSR_I, 1);; 555 556 #endif 557