Searched refs:R_QNC_SMBUS_HCLK (Results 1 – 2 of 2) sorted by relevance
102 IoWrite8 (IoPortBaseAddress + R_QNC_SMBUS_HCLK, V_QNC_SMBUS_HCLK_100KHZ); in InitializeInternal()
401 #define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W macro