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Searched refs:SCB_CCR_DIV_0_TRP_Pos (Results 1 – 4 of 4) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm3.h471 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB … macro
472 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB …
Dcore_sc300.h466 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB … macro
467 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB …
Dcore_cm4.h510 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB … macro
511 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB …
Dcore_cm7.h563 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB … macro
564 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB …