Home
last modified time | relevance | path

Searched refs:TCR (Results 1 – 5 of 5) sorted by relevance

/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/AArch64/
DAArch64Mmu.c581 UINT64 TCR; in ArmConfigureMmu() local
610 TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB; in ArmConfigureMmu()
614 TCR |= TCR_PS_4GB; in ArmConfigureMmu()
616 TCR |= TCR_PS_64GB; in ArmConfigureMmu()
618 TCR |= TCR_PS_1TB; in ArmConfigureMmu()
620 TCR |= TCR_PS_4TB; in ArmConfigureMmu()
622 TCR |= TCR_PS_16TB; in ArmConfigureMmu()
624 TCR |= TCR_PS_256TB; in ArmConfigureMmu()
632 TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1; in ArmConfigureMmu()
636 TCR |= TCR_IPS_4GB; in ArmConfigureMmu()
[all …]
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm3.h673 …__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register … member
1594 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ in ITM_SendChar()
Dcore_sc300.h653 …__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register … member
1574 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ in ITM_SendChar()
Dcore_cm4.h713 …__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register … member
1746 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ in ITM_SendChar()
Dcore_cm7.h894 …__IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register … member
2165 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ in ITM_SendChar()