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Searched refs:TER (Results 1 – 4 of 4) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm3.h669 …__IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register … member
1595 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ in ITM_SendChar()
Dcore_sc300.h649 …__IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register … member
1575 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ in ITM_SendChar()
Dcore_cm4.h709 …__IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register … member
1747 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ in ITM_SendChar()
Dcore_cm7.h890 …__IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register … member
2166 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ in ITM_SendChar()