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Searched refs:TPR (Results 1 – 4 of 4) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm3.h671 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
Dcore_sc300.h651 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
Dcore_cm4.h711 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member
Dcore_cm7.h892 …__IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register … member