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Searched refs:TrsRing (Results 1 – 5 of 5) sorted by relevance

/device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/
DDebugCommunicationLibUsb3Transfer.c29 IN TRANSFER_RING *TrsRing in XhcSyncTrsRing() argument
36 ASSERT (TrsRing != NULL); in XhcSyncTrsRing()
41 TrsTrb = (TRB_TEMPLATE *)(UINTN) TrsRing->RingEnqueue; in XhcSyncTrsRing()
45 for (Index = 0; Index < TrsRing->TrbNumber; Index++) { in XhcSyncTrsRing()
46 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) { in XhcSyncTrsRing()
55 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0; in XhcSyncTrsRing()
59 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1; in XhcSyncTrsRing()
63 ASSERT (Index != TrsRing->TrbNumber); in XhcSyncTrsRing()
65 if ((EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb != TrsRing->RingEnqueue) { in XhcSyncTrsRing()
66 TrsRing->RingEnqueue = (EFI_PHYSICAL_ADDRESS)(UINTN) TrsTrb; in XhcSyncTrsRing()
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/
DXhciSched.c2658 IN TRANSFER_RING *TrsRing in XhcPeiSyncTrsRing() argument
2664 ASSERT (TrsRing != NULL); in XhcPeiSyncTrsRing()
2668 TrsTrb = TrsRing->RingEnqueue; in XhcPeiSyncTrsRing()
2671 for (Index = 0; Index < TrsRing->TrbNumber; Index++) { in XhcPeiSyncTrsRing()
2672 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) { in XhcPeiSyncTrsRing()
2681 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0; in XhcPeiSyncTrsRing()
2685 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1; in XhcPeiSyncTrsRing()
2686 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address in XhcPeiSyncTrsRing()
2690 ASSERT (Index != TrsRing->TrbNumber); in XhcPeiSyncTrsRing()
2692 if (TrsTrb != TrsRing->RingEnqueue) { in XhcPeiSyncTrsRing()
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DXhciSched.h1221 IN TRANSFER_RING *TrsRing
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
DXhciSched.c1790 IN TRANSFER_RING *TrsRing in XhcSyncTrsRing() argument
1796 ASSERT (TrsRing != NULL); in XhcSyncTrsRing()
1800 TrsTrb = TrsRing->RingEnqueue; in XhcSyncTrsRing()
1803 for (Index = 0; Index < TrsRing->TrbNumber; Index++) { in XhcSyncTrsRing()
1804 if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) { in XhcSyncTrsRing()
1813 ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0; in XhcSyncTrsRing()
1817 TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1; in XhcSyncTrsRing()
1818 TrsTrb = (TRB_TEMPLATE *) TrsRing->RingSeg0; // Use host address in XhcSyncTrsRing()
1822 ASSERT (Index != TrsRing->TrbNumber); in XhcSyncTrsRing()
1824 if (TrsTrb != TrsRing->RingEnqueue) { in XhcSyncTrsRing()
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DXhciSched.h1233 TRANSFER_RING *TrsRing