1 /**
2 
3 Copyright (c) 2012  - 2014, Intel Corporation. All rights reserved
4 
5   This program and the accompanying materials are licensed and made available under
6   the terms and conditions of the BSD License that accompanies this distribution.
7   The full text of the license may be found at
8   http://opensource.org/licenses/bsd-license.php.
9 
10   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 
13 
14 
15   @file
16   PchRegsUsb.h
17 
18   @brief
19   Register names for PCH USB devices.
20 
21   Conventions:
22 
23   - Prefixes:
24     Definitions beginning with "R_" are registers
25     Definitions beginning with "B_" are bits within registers
26     Definitions beginning with "V_" are meaningful values of bits within the registers
27     Definitions beginning with "S_" are register sizes
28     Definitions beginning with "N_" are the bit position
29   - In general, PCH registers are denoted by "_PCH_" in register names
30   - Registers / bits that are different between PCH generations are denoted by
31     "_PCH_<generation_name>_" in register/bit names. e.g., "_PCH_VLV_"
32   - Registers / bits that are different between SKUs are denoted by "_<SKU_name>"
33     at the end of the register/bit names
34   - Registers / bits of new devices introduced in a PCH generation will be just named
35     as "_PCH_" without <generation_name> inserted.
36 
37 **/
38 #ifndef _PCH_REGS_USB_H_
39 #define _PCH_REGS_USB_H_
40 
41 ///
42 /// USB Definitions
43 ///
44 
45 typedef enum {
46   PchEhci1 = 0,
47   PchEhciControllerMax
48 } PCH_USB20_CONTROLLER_TYPE;
49 
50 #define PCH_USB_MAX_PHYSICAL_PORTS          4      /// Max Physical Connector EHCI + XHCI, not counting virtual ports like USB-R.
51 #define PCH_EHCI_MAX_PORTS                  4      /// Counting ports behind RMHs 8 from EHCI-1 and 6 from EHCI-2, not counting EHCI USB-R virtual ports.
52 #define PCH_HSIC_MAX_PORTS                  2
53 #define PCH_XHCI_MAX_USB3_PORTS             1
54 
55 #define PCI_DEVICE_NUMBER_PCH_USB           29
56 #define PCI_FUNCTION_NUMBER_PCH_EHCI        0
57 
58 #define R_PCH_USB_VENDOR_ID                 0x00  // Vendor ID
59 #define V_PCH_USB_VENDOR_ID                 V_PCH_INTEL_VENDOR_ID
60 
61 #define R_PCH_USB_DEVICE_ID                 0x02  // Device ID
62 #define V_PCH_USB_DEVICE_ID_0               0x0F34  // EHCI#1
63 
64 #define R_PCH_EHCI_SVID                     0x2C  // USB2 Subsystem Vendor ID
65 #define B_PCH_EHCI_SVID                     0xFFFF // USB2 Subsystem Vendor ID Mask
66 
67 #define R_PCH_EHCI_PWR_CNTL_STS             0x54  // Power Management Control / Status
68 #define B_PCH_EHCI_PWR_CNTL_STS_PME_STS     BIT15 // PME Status
69 #define B_PCH_EHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13) // Data Scale
70 #define B_PCH_EHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9) // Data Select
71 #define B_PCH_EHCI_PWR_CNTL_STS_PME_EN      BIT8  // Power Enable
72 #define B_PCH_EHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0) // Power State
73 #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D0  0     // D0 State
74 #define V_PCH_EHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0) // D3 Hot State
75 
76 ///
77 /// USB3 (XHCI) related definitions
78 ///
79 #define PCI_DEVICE_NUMBER_PCH_XHCI          20
80 #define PCI_FUNCTION_NUMBER_PCH_XHCI        0
81 //
82 /////
83 ///// XHCI PCI Config Space registers
84 /////
85 
86 #define R_PCH_XHCI_SVID                     0x2C
87 #define B_PCH_XHCI_SVID                     0xFFFF
88 
89 
90 #define R_PCH_XHCI_PWR_CNTL_STS             0x74
91 #define B_PCH_XHCI_PWR_CNTL_STS_PME_STS     BIT15
92 #define B_PCH_XHCI_PWR_CNTL_STS_DATASCL     (BIT14 | BIT13)
93 #define B_PCH_XHCI_PWR_CNTL_STS_DATASEL     (BIT12 | BIT11 | BIT10 | BIT9)
94 #define B_PCH_XHCI_PWR_CNTL_STS_PME_EN      BIT8
95 #define B_PCH_XHCI_PWR_CNTL_STS_PWR_STS     (BIT1 | BIT0)
96 #define V_PCH_XHCI_PWR_CNTL_STS_PWR_STS_D3  (BIT1 | BIT0)
97 
98 #endif
99