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/device/linaro/bootloader/edk2/ArmPlatformPkg/Include/Drivers/
DPL310L2Cache.h65 #define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup)) argument
66 #define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup) argument
67 #define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup) argument
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Dxe/EfiScriptLib/
DEfiScriptLib.c148 mBootScriptSave->Write ( in BootScriptSaveIoWrite()
198 mBootScriptSave->Write ( in BootScriptSaveIoReadWrite()
248 mBootScriptSave->Write ( in BootScriptSaveMemWrite()
298 mBootScriptSave->Write ( in BootScriptSaveMemReadWrite()
348 mBootScriptSave->Write ( in BootScriptSavePciCfgWrite()
398 mBootScriptSave->Write ( in BootScriptSavePciCfgReadWrite()
452 mBootScriptSave->Write ( in BootScriptSaveSmbusExecute()
498 mBootScriptSave->Write ( in BootScriptSaveStall()
536 mBootScriptSave->Write ( in BootScriptSaveDispatch()
587 mBootScriptSave->Write ( in BootScriptMemPoll()
[all …]
/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/ArmV7/
DArmV7Support.asm70 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
78 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
91 mcr p15, 0, r0, c1, c0, 0 ; Write control register
105 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
114 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
123 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
132 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
146 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
154 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
162 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
[all …]
DArmV7ArchTimerSupport.asm24 mcr p15, 0, r0, c14, c0, 0 ; Write to CNTFRQ
36 mcr p15, 0, r0, c14, c1, 0 ; Write to CNTK_CTL (Timer PL1 Control Register)
44 mcr p15, 0, r0, c14, c2, 0 ; Write to CNTP_TVAL (PL1 physical timer value register)
52 mcr p15, 0, r0, c14, c2, 1 ; Write to CNTP_CTL (PL1 Physical Timer Control Register)
60 mcr p15, 0, r0, c14, c3, 0 ; Write to CNTV_TVAL (Virtual Timer Value register)
68 mcr p15, 0, r0, c14, c3, 1 ; Write to CNTV_CTL (Virtual Timer Control Register)
80 mcrr p15, 2, r0, r1, c14 ; Write to CNTP_CTVAL (Physical Timer Compare Value Register)
96 mcrr p15, 4, r0, r1, c14 ; Write to CNTVOFF (Virtual Offset register)
DArmV7ArchTimerSupport.S44 mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ
56 mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)
64 mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)
72 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
80 mcr p15, 0, r0, c14, c3, 0 @ Write to CNTV_TVAL (Virtual Timer Value register)
88 mcr p15, 0, r0, c14, c3, 1 @ Write to CNTV_CTL (Virtual Timer Control Register)
100 mcrr p15, 2, r0, r1, c14 @ Write to CNTP_CTVAL (Physical Timer Compare Value Register)
116 mcrr p15, 4, r0, r1, c14 @ Write to CNTVOFF (Virtual Offset register)
DArmV7Support.S128 mcr p15, 0, r0, c1, c0, 0 @ Write control register
142 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
151 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
160 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
169 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
200 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
207 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
287 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
296 # Write back CPACR (Coprocessor Access Control Register)
/device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/Ia32/
DPcatIo.c57 return gCpuIo->Io.Write ( in PcatRootBridgeIoIoWrite()
87 IN BOOLEAN Write, in PcatRootBridgeIoPciRW() argument
172 This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned); in PcatRootBridgeIoPciRW()
173 if (Write) { in PcatRootBridgeIoPciRW()
174 This->Io.Write (This, Width, PciData, 1, UserBuffer); in PcatRootBridgeIoPciRW()
198 if (Write) { in PcatRootBridgeIoPciRW()
199 This->Mem.Write (This, Width, (UINTN) PciExpressRegAddr, 1, UserBuffer); in PcatRootBridgeIoPciRW()
353 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x26, 1, &Register); in CheckForRom()
354 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x2c, 1, &Register); in CheckForRom()
356 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x24, 1, &Register); in CheckForRom()
[all …]
/device/linaro/bootloader/edk2/DuetPkg/PciRootBridgeNoEnumerationDxe/X64/
DPcatIo.c57 return gCpuIo->Io.Write ( in PcatRootBridgeIoIoWrite()
87 IN BOOLEAN Write, in PcatRootBridgeIoPciRW() argument
172 This->Io.Write (This, EfiPciWidthUint32, PrivateData->PciAddress, 1, &PciAligned); in PcatRootBridgeIoPciRW()
173 if (Write) { in PcatRootBridgeIoPciRW()
174 This->Io.Write (This, Width, PciData, 1, UserBuffer); in PcatRootBridgeIoPciRW()
198 if (Write) { in PcatRootBridgeIoPciRW()
199 This->Mem.Write (This, Width, (UINTN) PciExpressRegAddr, 1, UserBuffer); in PcatRootBridgeIoPciRW()
353 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x26, 1, &Register); in CheckForRom()
354 IoDev->Pci.Write (IoDev, EfiPciWidthUint32, Address + 0x2c, 1, &Register); in CheckForRom()
356 IoDev->Pci.Write (IoDev, EfiPciWidthUint16, Address + 0x24, 1, &Register); in CheckForRom()
[all …]
/device/linaro/bootloader/edk2/DuetPkg/PciBusNoEnumerationDxe/
DPciEnumeratorSupport.c527 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); in GatherPPBInfo()
529 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); in GatherPPBInfo()
708 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne); in BarExisted()
714 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); in BarExisted()
1064 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); in InitializePPB()
1065 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1D, 1, &gAllZero); in InitializePPB()
1067 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x20, 1, &gAllOne); in InitializePPB()
1068 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x22, 1, &gAllZero); in InitializePPB()
1070 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x24, 1, &gAllOne); in InitializePPB()
1071 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint16, 0x26, 1, &gAllZero); in InitializePPB()
[all …]
DPciCommand.c82 return PciIo->Pci.Write ( in PciSetCommandRegister()
126 return PciIo->Pci.Write ( in PciEnableCommandRegister()
170 return PciIo->Pci.Write ( in PciDisableCommandRegister()
205 return PciIo->Pci.Write ( in PciSetBridgeControlRegister()
249 return PciIo->Pci.Write ( in PciEnableBridgeControlRegister()
292 return PciIo->Pci.Write ( in PciDisableBridgeControlRegister()
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/
DSDController.c278 PciIo->Mem.Write ( in SetHighSpeedMode()
313 PciIo->Mem.Write ( in SetDDRMode()
365 PciIo->Mem.Write ( in HostLEDEnable()
503 PciIo->Mem.Write ( in SendCommand()
513 PciIo->Mem.Write ( in SendCommand()
524 PciIo->Mem.Write ( in SendCommand()
549 PciIo->Mem.Write ( in SendCommand()
562 PciIo->Mem.Write ( in SendCommand()
573 PciIo->Mem.Write ( in SendCommand()
581 PciIo->Mem.Write ( in SendCommand()
[all …]
/device/linaro/bootloader/edk2/Omap35xxPkg/Library/RealTimeClockLib/
DRealTimeClockLib.c70 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1,… in LibGetTime()
156 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &D… in LibSetTime()
160 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &… in LibSetTime()
164 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Da… in LibSetTime()
168 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &D… in LibSetTime()
172 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, … in LibSetTime()
176 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, … in LibSetTime()
260 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1,… in LibRtcInitialize()
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Library/RealTimeClockLib/
DRealTimeClockLib.c70 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1,… in LibGetTime()
156 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, YEARS_REG), 1, &D… in LibSetTime()
160 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MONTHS_REG), 1, &… in LibSetTime()
164 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, DAYS_REG), 1, &Da… in LibSetTime()
168 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, HOURS_REG), 1, &D… in LibSetTime()
172 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, MINUTES_REG), 1, … in LibSetTime()
176 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, SECONDS_REG), 1, … in LibSetTime()
260 …Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, RTC_CTRL_REG), 1,… in LibRtcInitialize()
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Smm/SmmScriptLib/
DSmmScriptLib.c55 return mS3SmmSaveState->Write ( in BootScriptIoWrite()
89 return mS3SmmSaveState->Write ( in BootScriptIoReadWrite()
123 return mS3SmmSaveState->Write ( in BootScriptMemReadWrite()
157 return mS3SmmSaveState->Write ( in BootScriptPciCfgReadWrite()
191 return mS3SmmSaveState->Write ( in BootScriptPciCfgWrite()
219 return mS3SmmSaveState->Write ( in BootScriptStall()
244 return mS3SmmSaveState->Write ( in BootScriptDispatch()
275 return mS3SmmSaveState->Write ( in BootScriptMemWrite()
/device/linaro/bootloader/edk2/MdeModulePkg/Universal/FaultTolerantWriteDxe/
DFaultTolerantWriteDxe.uni2 // Fault Tolerant Write Dxe Driver.
4 // This driver installs Fault Tolerant Write (FTW) protocol,
20 #string STR_MODULE_ABSTRACT #language en-US "Fault Tolerant Write Dxe Driver."
22 #string STR_MODULE_DESCRIPTION #language en-US "Installs Fault Tolerant Write (FTW) protoc…
DSmmFaultTolerantWriteDxe.uni2 // Fault Tolerant Write Smm Driver.
4 // This driver installs SMM Fault Tolerant Write (FTW) protocol, which provides fault
21 #string STR_MODULE_ABSTRACT #language en-US "Fault Tolerant Write Smm Driver."
23 #string STR_MODULE_DESCRIPTION #language en-US "Installs SMM Fault Tolerant Write (FTW) pr…
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Compatibility/BootScriptSaveOnS3SaveStateThunk/
DScriptSave.c102 return mS3SaveState->Write ( in BootScriptIoWrite()
136 return mS3SaveState->Write ( in BootScriptIoReadWrite()
171 return mS3SaveState->Write ( in BootScriptMemWrite()
206 return mS3SaveState->Write ( in BootScriptMemReadWrite()
241 return mS3SaveState->Write ( in BootScriptPciCfgWrite()
276 return mS3SaveState->Write ( in BootScriptPciCfgReadWrite()
312 return mS3SaveState->Write ( in BootScriptPciCfg2Write()
350 return mS3SaveState->Write ( in BootScriptPciCfg2ReadWrite()
389 return mS3SaveState->Write ( in BootScriptSmbusExecute()
419 return mS3SaveState->Write ( in BootScriptStall()
[all …]
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciBusDxe/
DPciResourceSupport.c1322 PciIo->Pci.Write ( in ProgramBar()
1339 PciIo->Pci.Write ( in ProgramBar()
1349 PciIo->Pci.Write ( in ProgramBar()
1404 PciIo->Pci.Write ( in ProgramVfBar()
1420 PciIo->Pci.Write ( in ProgramVfBar()
1430 PciIo->Pci.Write ( in ProgramVfBar()
1500 PciIo->Pci.Write ( in ProgramPpbApperture()
1517 PciIo->Pci.Write ( in ProgramPpbApperture()
1527 PciIo->Pci.Write ( in ProgramPpbApperture()
1547 PciIo->Pci.Write ( in ProgramPpbApperture()
[all …]
DPciEnumeratorSupport.c580 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); in GatherPpbInfo()
582 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); in GatherPpbInfo()
605 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Value); in GatherPpbInfo()
607 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &Temp); in GatherPpbInfo()
813 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT32)Offset, 1, &gAllOne); in VfBarExisted()
819 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT32)Offset, 1, &OriginalValue); in VfBarExisted()
878 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &gAllOne); in BarExisted()
884 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, (UINT8) Offset, 1, &OriginalValue); in BarExisted()
1949 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint32, Offset, 1, &gAllOne); in InitializePciDevice()
1973 PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x1C, 1, &gAllOne); in InitializePpb()
[all …]
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/
DPciDevice.c147 Status = PciIo->Pci.Write (
190 Status = PciIo->Pci.Write (
216 Status = PciIo->Pci.Write (
245 Status = PciIo->Pci.Write (
281 Status = PciIo->Pci.Write (
298 Status = PciIo->Pci.Write (
326 Status = PciIo->Pci.Write (
482 Status = PciIo->Pci.Write ( in PciBusEvent()
/device/linaro/bootloader/edk2/MdeModulePkg/Universal/Disk/DiskIoDxe/
DDiskIo.c424 (Task->Token != NULL) && !Subtask->Write in DiskIo2OnReadWriteComplete()
463 IN BOOLEAN Write, in DiskIoCreateSubtask() argument
480 Subtask->Write = Write; in DiskIoCreateSubtask()
503 Write ? 'W': 'R', Lba, Offset, Length, WorkingBuffer, Buffer in DiskIoCreateSubtask()
527 IN BOOLEAN Write, in DiskIoCreateSubtaskList() argument
564 Subtask = DiskIoCreateSubtask (Write, Lba, UnderRun, 0, NULL, BufferPtr, Blocking); in DiskIoCreateSubtaskList()
582 if (Write) { in DiskIoCreateSubtaskList()
594 … Subtask = DiskIoCreateSubtask (Write, Lba, UnderRun, Length, WorkingBuffer, BufferPtr, Blocking); in DiskIoCreateSubtaskList()
618 if (Write) { in DiskIoCreateSubtaskList()
630 …Subtask = DiskIoCreateSubtask (Write, OverRunLba, 0, OverRun, WorkingBuffer, BufferPtr + BufferSiz… in DiskIoCreateSubtaskList()
[all …]
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/
DCEATA.c41 IN BOOLEAN Write, in ReadWriteMultipleRegister() argument
56 if (Write) { in ReadWriteMultipleRegister()
61 if (Write) { in ReadWriteMultipleRegister()
116 IN BOOLEAN Write, in ReadWriteMultipleBlock() argument
132 if (Write) { in ReadWriteMultipleBlock()
266 IN BOOLEAN Write, in SendATACommand() argument
325 Write, in SendATACommand()
/device/linaro/bootloader/edk2/QuarkPlatformPkg/Pci/Dxe/PciHostBridge/
DPciHostBridgeSupport.c85 mPciRootBridgeIo->Pci.Write ( in ChipsetPreprocessController()
99 mPciRootBridgeIo->Pci.Write ( in ChipsetPreprocessController()
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/
DMisc.c141 Status = CpuIoPpi->Io.Write ( in EfiCommonIoWrite()
162 Status = RootBridgeIo->Io.Write (RootBridgeIo, Width, Address, Count, Buffer); in EfiCommonIoWrite()
267 Status = PciCfgPpi->Write ( in EfiCommonPciWrite()
295 Status = RootBridgeIo->Pci.Write ( in EfiCommonPciWrite()
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UhciDxe/
DUhciReg.c73 Status = PciIo->Io.Write ( in UhciWriteReg()
244 Status = PciIo->Io.Write ( in UhciSetFrameListBaseAddr()
274 PciIo->Pci.Write ( in UhciTurnOffUsbEmulation()

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