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/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/
DPchXhci.asl75 PR2, 32, //bit[8:0] USB2HCSEL
76 PR2M, 32, //bit[8:0] USB2HCSELM
77 PR3, 32, //bit[3:0] USB3SSEN
78 PR3M, 32 //bit[3:0] USB3SSENM
114 …//95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 C…
115 …// bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info'…
117 … //127:96 -bit[96]=1 Ejectable bit[97]=1 OSPM Ejection required Bit[105:98]=0 no Cabinet Number
118 …// bit[113:106]=0 no Card cage Number bit[114]=0 no reference shape Bit[118:115]=0 no r…
153 …//95:64 - bit[66:64]=b'011 visiable/docking/no lid bit[69:67]=b'001 bottom panel bit[71:70]=b'01 C…
154 …// bit[77:74]=6 Horizontal Trapezoid bit[78]=0 bit[86:79]=0 bit[94:87]='0 no group info'…
[all …]
/device/linaro/bootloader/edk2/StdLib/LibC/String/
DSearching.c66 unsigned char bit; in BuildBitmap() local
76 bit = WHICH_BIT(*s2); in BuildBitmap()
77 bitmap[index] = bitmap[index] | bit; in BuildBitmap()
92 UINT8 bit; in strcspn() local
101 bit = WHICH_BIT(*str); in strcspn()
102 if ((bitmap[index] & bit) != 0) in strcspn()
118 UINT8 bit; in strpbrk() local
125 bit = WHICH_BIT(*s1); in strpbrk()
126 if( (bitmap[index] & bit) != 0) { in strpbrk()
165 UINT8 bit; in strspn() local
[all …]
/device/linaro/bootloader/edk2/StdLib/LibC/Wchar/
DSearching.c61 UINT8 bit; in BuildBitmap() local
73 bit = WHICH_BIT(*s2); in BuildBitmap()
74 bitmap[index] |= bit; in BuildBitmap()
87 UINT8 bit; in wcscspn() local
98 bit = WHICH_BIT(*str); in wcscspn()
99 if ((__wchar_bitmap[index] & bit) != 0) in wcscspn()
115 UINT8 bit; in wcspbrk() local
122 bit = WHICH_BIT(*s1); in wcspbrk()
123 if( (__wchar_bitmap[index] & bit) != 0) { in wcspbrk()
158 UINT8 bit; in wcsspn() local
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/device/linaro/bootloader/edk2/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/
DSecEntry.S70 # rdtsc load 64bit time-stamp counter to EDX:EAX
84 # Transition to 16 bit protected mode
87 orl $0x00000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
91 orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
262 .byte 0xCF # page-granular, 32-bit
272 .byte 0xCF # page-granular, 32-bit
282 .byte 0xCF # page-granular, 32-bit
293 .byte 0xCF # page-granular, 32-bit
303 .byte 0x00 # byte-granular, 16-bit
313 .byte 0x00 # byte-granular, 16-bit
[all …]
DSecEntry.asm78 ; rdtsc load 64bit time-stamp counter to EDX:EAX
92 ; Transition to 16 bit protected mode
95 or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
99 or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
275 DB 0CFh ; page-granular, 32-bit
285 DB 0CFh ; page-granular, 32-bit
295 DB 0CFh ; page-granular, 32-bit
306 DB 0CFh ; page-granular, 32-bit
316 DB 00h ; byte-granular, 16-bit
326 DB 00h ; byte-granular, 16-bit
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/device/google/contexthub/firmware/os/inc/
DhostIntf.h74 void hostIntfSetInterrupt(uint32_t bit);
75 bool hostIntfGetInterrupt(uint32_t bit);
76 void hostIntfClearInterrupt(uint32_t bit);
77 void hostIntfSetInterruptMask(uint32_t bit);
78 bool hostIntfGetInterruptMask(uint32_t bit);
79 void hostIntfClearInterruptMask(uint32_t bit);
/device/linaro/bootloader/edk2/StdLib/LibC/Softfloat/bits32/
Dsoftfloat-macros35 bits are shifted off, they are ``jammed'' into the least significant bit of
36 the result by setting the least significant bit to 1. The value of `count'
61 Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
64 than 64, the result will be 0. The result is broken into two 32-bit pieces
94 Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
96 are ``jammed'' into the least significant bit of the result by setting the
97 least significant bit to 1. The value of `count' can be arbitrarily large;
100 nonzero. The result is broken into two 32-bit pieces which are stored at
138 Shifts the 96-bit value formed by concatenating `a0', `a1', and `a2' right
140 at most 64 nonzero bits; these are broken into two 32-bit pieces which are
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmSoftFloatLib/bits32/
Dsoftfloat-macros35 bits are shifted off, they are ``jammed'' into the least significant bit of
36 the result by setting the least significant bit to 1. The value of `count'
61 Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
64 than 64, the result will be 0. The result is broken into two 32-bit pieces
94 Shifts the 64-bit value formed by concatenating `a0' and `a1' right by the
96 are ``jammed'' into the least significant bit of the result by setting the
97 least significant bit to 1. The value of `count' can be arbitrarily large;
100 nonzero. The result is broken into two 32-bit pieces which are stored at
138 Shifts the 96-bit value formed by concatenating `a0', `a1', and `a2' right
140 at most 64 nonzero bits; these are broken into two 32-bit pieces which are
[all …]
/device/linaro/bootloader/edk2/StdLib/LibC/Softfloat/bits64/
Dsoftfloat-macros36 bits are shifted off, they are ``jammed'' into the least significant bit of
37 the result by setting the least significant bit to 1. The value of `count'
63 bits are shifted off, they are ``jammed'' into the least significant bit of
64 the result by setting the least significant bit to 1. The value of `count'
89 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by 64
92 bits shifted off form a second 64-bit result as follows: The _last_ bit
93 shifted off is the most-significant bit of the extra result, and the other
136 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
139 than 128, the result will be 0. The result is broken into two 64-bit pieces
169 Shifts the 128-bit value formed by concatenating `a0' and `a1' right by the
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/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/FspSupport/Library/SecFspPlatformSecLibVlv2/Ia32/
DSecEntry.asm77 ; rdtsc load 64bit time-stamp counter to EDX:EAX
91 ; Transition to 16 bit protected mode
94 or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
98 or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
/device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/PlatformSecLib/Ia32/
DFlat32.asm40 ; CR0 cache control bit definition
56 ; Contrary to the name, this file contains 16 bit code as well.
112 ; Transition to 16 bit protected mode
115 or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
301 …jz TestHmboundLock ; Zero means bit clear, we're not requested to cold reset so continue as nor…
311 jz ConfigHmbound ; Zero means bit clear, we have the config we want so continue as normal
313 ; Failed to config - store sticky bit debug
317 or eax, RESET_FOR_HMBOUND_LOCK ; Set the bit we're interested in
351 jnz ConfigPci ; Non-zero means bit set, we have the config we want so continue as normal
353 ; Failed to config - store sticky bit debug
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/device/linaro/bootloader/edk2/UefiCpuPkg/ResetVector/Vtf0/
DMain.asm34 ; Transition the processor from 16-bit real mode to 32-bit flat mode
67 ; Jump to the 32-bit SEC entry point
74 ; Transition the processor from 32-bit flat mode to 64-bit flat mode
81 ; Some values were calculated in 32-bit mode. Make sure the upper
82 ; 32-bits of 64-bit registers are zero for these values.
100 ; Jump to the 64-bit SEC entry point
/device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/Ia32/
DRdRand.asm18 ; Generates random number through CPU RdRand instruction under 32-bit platform.
30 ; Generates a 16 bit random number through RDRAND instruction.
36 ; rdrand ax ; generate a 16 bit RN into ax
50 ; Generates a 32 bit random number through RDRAND instruction.
56 ; rdrand eax ; generate a 32 bit RN into eax
70 ; Generates a 64 bit random number through RDRAND instruction.
76 ; rdrand eax ; generate a 32 bit RN into eax
83 db 0fh, 0c7h, 0f0h ; generate another 32 bit RN
/device/linaro/bootloader/edk2/IntelFspPkg/Library/SecFspSecPlatformLibNull/Ia32/
DFlat32.s21 # Contrary to the name, this file contains 16 bit code as well.
59 # Transition to 16 bit protected mode
62 … 0x66,0x83,0xc8,0x03 #orl $0x0000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
DFlat32.asm26 ; Contrary to the name, this file contains 16 bit code as well.
64 ; Transition to 16 bit protected mode
67 or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
/device/linaro/bootloader/edk2/MdePkg/Library/BaseLib/X64/
DRdRand.asm18 ; Generates random number through CPU RdRand instruction under 64-bit platform.
27 ; Generates a 16 bit random number through RDRAND instruction.
33 ; rdrand ax ; generate a 16 bit RN into eax,
46 ; Generates a 32 bit random number through RDRAND instruction.
52 ; rdrand eax ; generate a 32 bit RN into eax,
65 ; Generates a 64 bit random number through one RDRAND instruction.
71 ; rdrand rax ; generate a 64 bit RN into rax,
/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Modules/
Dimageop.c277 int i, bit; in imageop_grey2mono() local
291 bit = 0x80; in imageop_grey2mono()
295 ovalue |= bit; in imageop_grey2mono()
296 bit >>= 1; in imageop_grey2mono()
297 if ( bit == 0 ) { in imageop_grey2mono()
299 bit = 0x80; in imageop_grey2mono()
303 if ( bit != 0x80 ) in imageop_grey2mono()
389 int i, bit; in imageop_dither2mono() local
403 bit = 0x80; in imageop_dither2mono()
410 ovalue |= bit; in imageop_dither2mono()
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/device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/ArmV7/
DArmV7Support.asm69 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
77 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
102 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
104 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
111 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
113 bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
120 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
122 orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
129 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
131 BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
[all …]
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EfiCommonLib/Ia32/
DDivU64x32.c55 mov eax, dword ptr Dividend[4] ; Put high 32 bits of 64-bit dividend in EAX in DivU64x32()
62 mov eax, dword ptr Dividend[0] ; Put low 32 bits of 64-bit dividend in EAX in DivU64x32()
63 div ecx ; Leave the REMAINDER in EDX as High 32-bit of new dividend in DivU64x32()
73 pop edx ; Pop High 32-bit QUOITENT to EDX in DivU64x32()
DDivU64x32.S69 movl 0xC(%ebp), %eax # Put high 32 bits of 64-bit dividend in EAX
76 movl 8(%ebp), %eax # Put low 32 bits of 64-bit dividend in EAX
77 divl %ecx # Leave the REMAINDER in EDX as High 32-bit of new dividend
87 popl %edx # Pop High 32-bit QUOITENT to EDX
DDivU64x32.asm63 mov eax, [ebp + 0Ch] ; Put high 32 bits of 64-bit dividend in EAX
70 mov eax, [ebp + 8] ; Put low 32 bits of 64-bit dividend in EAX
71 div ecx ; Leave the REMAINDER in EDX as High 32-bit of new dividend
81 pop edx ; Pop High 32-bit QUOITENT to EDX
/device/linaro/bootloader/edk2/StdLib/LibC/CRT/Ia32/
Dmulll.S18 # 64-bit Math Worker Function.
19 # Multiplies a 64-bit signed or unsigned value by a 64-bit signed or unsigned value
20 # and returns a 64-bit result
Dudivdi3.S18 # 64-bit Math Worker Function.
19 # Divides a 64-bit unsigned value with a 64-bit unsigned value and returns
20 # a 64-bit unsigned result.
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/X64/
DThunk16.asm76 ; in opcode since 64-bit MASM prevents accesses to those registers.
110 ; rsi in the following 2 instructions is indeed bp in 16-bit code
126 ; rdi in the instruction below is indeed bx in 16-bit code
173 mov ss, esi ; set up 16-bit stack segment
174 mov sp, bx ; set up 16-bit stack pointer
175 DB 66h ; make the following call 32-bit
180 lea eax, [rsi + (@RealMode - @Base)] ; rsi is "bp" in 16-bit code
193 DB 66h ; make the following retf 32-bit
207 DB 8fh ; 16-bit segment, 4GB limit
214 DB 8fh ; 16-bit segment, 4GB limit
[all …]
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Thunk16/Ia32/
DThunk16.asm40 DB 8fh ; 16-bit segment
47 DB 8fh ; 16-bit segment
100 add edi, eax ; edi <- linear address of 16-bit stack
103 rep movsd ; copy context to 16-bit stack
109 pop ebx ; ebx <- 16-bit stack offset
128 mov edi, edx ; edi <- 16-bit stack segment
134 lgdt _16Gdtr ; load 16-bit GDTR
147 add eax, esp ; eax <- address of 16-bit stack

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