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Searched refs:isbM32m (Results 1 – 3 of 3) sorted by relevance

/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dmeminit.c165 isbM32m(MCU, PMSTS, BIT0, BIT0); in clear_self_refresh()
229 isbM32m(MCU, DRMC, BIT16, BIT16); in perform_ddr_reset()
301 isbM32m(MCU, DPMC1, 2 << 4, BIT5|BIT4); in prog_ddr_control()
520 …isbM32m(DDRPHY, (CMDPMCONFIG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT20, BIT20); // SPID_INIT_CO… in ddrphy_init()
522 … isbM32m(DDRPHY, (CMDCFGREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT2, BIT2); // IOBUFACTRST_N=0 in ddrphy_init()
524 isbM32m(DDRPHY, (CMDPTRREG + (channel_i * DDRIOCCC_CH_OFFSET)), ~BIT0, BIT0); // WRPTRENABLE=0 in ddrphy_init()
529 isbM32m(DDRPHY, MASTERRSTN, 0, BIT0); // PHYRSTN=0 in ddrphy_init()
539 …isbM32m(DDRPHY, (DQOBSCKEBBCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET))… in ddrphy_init()
548 …isbM32m(DDRPHY, (B0RXIOBUFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)),… in ddrphy_init()
549 …isbM32m(DDRPHY, (B1RXIOBUFCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)),… in ddrphy_init()
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Dmeminit_utils.c63 isbM32m(DDRPHY, reg, tempD, msk); in set_rcvn()
75 isbM32m(DDRPHY, reg, tempD, msk); in set_rcvn()
95 isbM32m(DDRPHY, reg, tempD, msk); in set_rcvn()
174 isbM32m(DDRPHY, reg, tempD, msk); in set_rdqs()
240 isbM32m(DDRPHY, reg, tempD, msk); in set_wdqs()
252 isbM32m(DDRPHY, reg, tempD, msk); in set_wdqs()
272 isbM32m(DDRPHY, reg, tempD, msk); in set_wdqs()
351 isbM32m(DDRPHY, reg, tempD, msk); in set_wdq()
363 isbM32m(DDRPHY, reg, tempD, msk); in set_wdq()
383 isbM32m(DDRPHY, reg, tempD, msk); in set_wdq()
[all …]
Dio.h101 #define isbM32m WrMask32 macro