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Searched refs:tCL (Results 1 – 10 of 10) sorted by relevance

/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
Dmrc.h83 uint8_t tCL; // CAS latency in clocks member
Dmeminit.c415 TCL = mrc_params->params.tCL; // CAS latency in clocks in prog_ddr_timing_control()
431 Dtr0.field.tCL = TCL - 5; //Convert from TCL (DRAM clocks) to VLV indx in prog_ddr_timing_control()
474 …Dtr4.field.RDODTSTRT = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2; //Convert from WL (… in prog_ddr_timing_control()
475 Dtr4.field.RDODTSTOP = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2; in prog_ddr_timing_control()
507 tCAS = mrc_params->params.tCL; in ddrphy_init()
1037 mrs0Command.field.casLatency = DTR0reg.field.tCL + 1; in jedec_init()
Dgen5_iosf_sb_definitions.h82 uint32_t tCL :3; /**< bit [14:12] CAS Latency */ member
/device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/
DDdrMemoryController.h184 unsigned tCL :2; /**< CAS Latency (3,4,5,6) */ member
/device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/
DMrcWrapper.h125 UINT8 tCL; ///< DRAM CAS Latency in clocks. member
DMrcWrapper.c133 MrcData->params.tCL = ItemData->tCL; in MrcConfigureFromInfoHob()
154 MrcData->params.tCL, in MrcConfigureFromInfoHob()
/device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/
DVlv2DeviceRefCodePkg.dec211 ## tCL.<BR><BR>
212 # @Prompt tCL
/device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/
DPlatformPkgIA32.dsc789 ## tCL.<BR><BR>
790 # @Prompt tCL
DPlatformPkgGccX64.dsc789 ## tCL.<BR><BR>
790 # @Prompt tCL
DPlatformPkgX64.dsc789 ## tCL.<BR><BR>
790 # @Prompt tCL