| /external/llvm/test/CodeGen/MIR/ARM/ |
| D | imm-peephole-arm.mir | 4 # CHECK: [[SUM1TMP:%.*]] = ADDri [[IN]], 133
5 # CHECK: [[SUM1:%.*]] = ADDri killed [[SUM1TMP]], 25600
13 # CHECK: [[SUM4TMP:%.*]] = ADDri killed [[IN]], 133
14 # CHECK: [[SUM4:%.*]] = ADDri killed [[SUM4TMP]], 25600
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| D | cfi-same-value.mir | 77 %sp = ADDri killed %sp, 40, 14, _, _
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcFrameLowering.cpp | 45 unsigned ADDri) const { in emitSPAdjustment()
52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
119 SAVEri = SP::ADDri; in emitPrologue()
196 emitSPAdjustment(MF, MBB, I, Size, SP::ADDrr, SP::ADDri); in eliminateCallFramePseudoInstr()
222 emitSPAdjustment(MF, MBB, MBBI, NumBytes, SP::ADDrr, SP::ADDri); in emitEpilogue()
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| D | SparcFrameLowering.h | 62 int NumBytes, unsigned ADDrr, unsigned ADDri) const;
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| D | DelaySlotFiller.cpp | 507 case SP::ADDri: return combineRestoreADD(MBBI, PrevInst, TII); break; in tryCombineRestoreWithPrevInst()
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| D | SparcInstrAliases.td | 387 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
390 def : InstAlias<"inc $simm13, $rd", (ADDri IntRegs:$rd, IntRegs:$rd, i32imm:$simm13), 0>;
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| D | SparcInstrInfo.td | 1620 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1629 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1630 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1632 (ADDri $r, tblockaddress:$in)>;
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| /external/llvm/lib/CodeGen/ |
| D | README.txt | 35 %reg1037 = ADDri %reg1039, 1
43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
45 PHI node. We should treat it as a two-address code and make sure the ADDri is
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | README.txt | 35 %reg1037 = ADDri %reg1039, 1
43 Note ADDri is not a two-address instruction. However, its result %reg1037 is an
45 PHI node. We should treat it as a two-address code and make sure the ADDri is
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | crash-O0.ll | 17 ; This function uses the scavenger for an ADDri instruction.
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| /external/llvm/test/CodeGen/ARM/ |
| D | crash-O0.ll | 17 ; This function uses the scavenger for an ADDri instruction.
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcRegisterInfo.cpp | 68 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size); in eliminateCallFramePseudoInstr()
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| D | SparcAsmPrinter.cpp | 78 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri) && in printOperand()
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| D | SparcInstrInfo.td | 805 (ADDri IntRegs:$r, tglobaladdr:$in)>;
807 (ADDri IntRegs:$r, tconstpool:$in)>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMMCInstLower.cpp | 123 case ARM::ADDri: in LowerARMMachineInstrToMCInst()
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| D | ARMBaseInstrInfo.cpp | 168 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
202 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
1964 {ARM::ADDSri, ARM::ADDri},
2026 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
2155 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
2487 case ARM::ADDri: in optimizeCompareInstr()
2698 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri; in FoldImmediate()
2701 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri; in FoldImmediate()
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| D | ARMAsmPrinter.cpp | 1211 case ARM::ADDri: in EmitUnwindingInstruction()
1799 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in EmitInstruction()
1826 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri) in EmitInstruction()
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| D | ARMBaseRegisterInfo.cpp | 589 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : in materializeFrameBaseRegister()
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| D | ARMFrameLowering.cpp | 1242 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in emitAlignedDPRCS2Restores()
1383 if (MI.getOpcode() == ARM::ADDri) { in estimateRSStackSizeLimit()
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| D | ARMLoadStoreOptimizer.cpp | 673 isThumb1 ? ARM::tADDi8 : ARM::ADDri; in CreateLoadStoreMulti()
1136 case ARM::ADDri: Scale = 1; CheckCPSRDef = true; break; in isIncrementOrDecrement()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 172 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
195 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
1470 {ARM::ADDSri, ARM::ADDri},
1528 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
1549 if (Opcode == ARM::ADDri) { in rewriteARMFrameIndex()
1801 case ARM::ADDri: in OptimizeCompareInstr()
1926 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break; in FoldImmediate()
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| D | ARMFrameLowering.cpp | 204 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; in emitPrologue()
818 if (I->getOpcode() == ARM::ADDri) { in estimateRSStackSizeLimit()
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| D | ARMAsmPrinter.cpp | 1119 case ARM::ADDri: in EmitUnwindingInstruction()
1743 TmpInst.setOpcode(ARM::ADDri); in EmitInstruction()
1780 TmpInst.setOpcode(ARM::ADDri); in EmitInstruction()
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| D | ARMLoadStoreOptimizer.cpp | 333 int BaseOpc = !isThumb2 ? ARM::ADDri : ARM::t2ADDri; in MergeOps()
540 MI->getOpcode() != ARM::ADDri) in isMatchingIncrement()
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| D | ARMFastISel.cpp | 674 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in TargetMaterializeAlloca()
860 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress()
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