| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 23 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : in AMDGPUTargetLowering() function in AMDGPUTargetLowering
48 SDValue AMDGPUTargetLowering::LowerFormalArguments( in LowerFormalArguments()
64 SDValue AMDGPUTargetLowering::LowerReturn( in LowerReturn()
79 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) in LowerOperation()
101 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, in LowerINTRINSIC_WO_CHAIN()
149 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op, in LowerIntrinsicIABS()
163 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op, in LowerIntrinsicLRP()
180 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op, in LowerUDIVREM()
291 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const in isHWTrueValue()
302 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const in isHWFalseValue()
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| D | AMDILISelLowering.cpp | 47 void AMDGPUTargetLowering::InitAMDILLowering() in InitAMDILLowering()
243 AMDGPUTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, in getTgtMemIntrinsic()
250 AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const in isFPImmLegal()
261 AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const in ShouldShrinkFPConstant()
277 AMDGPUTargetLowering::computeMaskedBitsForTargetNode( in computeMaskedBitsForTargetNode()
317 AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const in LowerSDIV()
335 AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const in LowerSREM()
354 AMDGPUTargetLowering::LowerBUILD_VECTOR( SDValue Op, SelectionDAG &DAG ) const in LowerBUILD_VECTOR()
420 AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const in LowerSIGN_EXTEND_INREG()
451 AMDGPUTargetLowering::genIntType(uint32_t size, uint32_t numEle) const in genIntType()
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| D | AMDGPUTargetMachine.h | 36 AMDGPUTargetLowering * TLInfo;
58 virtual AMDGPUTargetLowering * getTargetLowering() const { in getTargetLowering()
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| D | AMDGPUISelLowering.h | 24 class AMDGPUTargetLowering : public TargetLowering
42 AMDGPUTargetLowering(TargetMachine &TM);
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| D | SIISelLowering.cpp | 27 AMDGPUTargetLowering(TM), in SITargetLowering()
79 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
264 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
277 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
443 default: return AMDGPUTargetLowering::getTargetNodeName(Opcode); in getTargetNodeName()
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| D | R600ISelLowering.h | 23 class R600TargetLowering : public AMDGPUTargetLowering
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| D | R600ISelLowering.cpp | 26 AMDGPUTargetLowering(TM), in R600TargetLowering()
61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
248 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
280 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
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| D | SIISelLowering.h | 22 class SITargetLowering : public AMDGPUTargetLowering
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) { in getEquivalentMemType()
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) { in getEquivalentBitType()
66 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, in AMDGPUTargetLowering() function in AMDGPUTargetLowering
491 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const { in getVectorIdxTy()
495 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const { in isSelectSupported()
501 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { in isFPImmLegal()
507 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const { in ShouldShrinkFPConstant()
512 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N, in shouldReduceLoadWidth()
535 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy, in isLoadBitCastBeneficial()
554 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const { in isCheapToSpeculateCttz()
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| D | AMDGPUTargetTransformInfo.h | 26 class AMDGPUTargetLowering; variable
34 const AMDGPUTargetLowering *TLI;
37 const AMDGPUTargetLowering *getTLI() const { return TLI; } in getTLI()
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| D | AMDGPUCallLowering.h | 22 class AMDGPUTargetLowering; variable
26 AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
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| D | AMDGPUCallLowering.cpp | 28 AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI) in AMDGPUCallLowering()
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| D | AMDGPUSubtarget.h | 121 const AMDGPUTargetLowering *getTargetLowering() const override;
446 inline const AMDGPUTargetLowering *AMDGPUSubtarget::getTargetLowering() const { in getTargetLowering()
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| D | AMDGPUISelLowering.h | 27 class AMDGPUTargetLowering : public TargetLowering {
121 AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
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| D | R600ISelLowering.h | 25 class R600TargetLowering final : public AMDGPUTargetLowering {
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| D | R600ISelLowering.cpp | 35 : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) { in R600TargetLowering()
238 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
616 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
671 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
833 AMDGPUTargetLowering::ReplaceNodeResults(N, Results, DAG); in ReplaceNodeResults()
921 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1355 if (SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG)) in LowerSTORE()
1953 default: return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
2070 if (SDValue Ret = AMDGPUTargetLowering::PerformDAGCombine(N, DCI)) in PerformDAGCombine()
2166 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
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| D | SIISelLowering.h | 23 class SITargetLowering final : public AMDGPUTargetLowering {
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| D | SIISelLowering.cpp | 57 : AMDGPUTargetLowering(TM, STI) { in SITargetLowering()
947 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs, in LowerReturn()
1159 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); in EmitInstrWithCustomInserter()
1230 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
1567 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG); in LowerGlobalAddress()
1915 return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerINTRINSIC_WO_CHAIN()
2522 if (SDValue Base = AMDGPUTargetLowering::performAndCombine(N, DCI)) in performAndCombine()
2865 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
3061 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI); in PerformDAGCombine()
3378 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT); in CreateLiveInRegister()
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| D | AMDGPUISelDAGToDAG.cpp | 1551 const AMDGPUTargetLowering& Lowering = in PostprocessISelDAG()
1552 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering()); in PostprocessISelDAG()
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