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/external/boringssl/src/ssl/test/runner/curve25519/
Dladderstep_amd64.s32 MOVQ SI,AX
37 ADDQ ·_2P0(SB),AX
47 SUBQ 80(DI),AX
57 MOVQ AX,96(SP)
62 MOVQ 96(SP),AX
64 MOVQ AX,SI
66 MOVQ 96(SP),AX
67 SHLQ $1,AX
69 MOVQ AX,R8
71 MOVQ 96(SP),AX
[all …]
Dmul_amd64.s32 IMUL3Q $19,DX,AX
33 MOVQ AX,64(SP)
35 MOVQ AX,R8
38 IMUL3Q $19,DX,AX
39 MOVQ AX,72(SP)
41 ADDQ AX,R8
43 MOVQ 0(SI),AX
45 ADDQ AX,R8
47 MOVQ 0(SI),AX
49 MOVQ AX,R10
[all …]
Dsquare_amd64.s28 MOVQ 0(SI),AX
30 MOVQ AX,CX
32 MOVQ 0(SI),AX
33 SHLQ $1,AX
35 MOVQ AX,R9
37 MOVQ 0(SI),AX
38 SHLQ $1,AX
40 MOVQ AX,R11
42 MOVQ 0(SI),AX
43 SHLQ $1,AX
[all …]
Dfreeze_amd64.s32 MOVQ ·REDMASK51(SB),AX
33 MOVQ AX,R10
39 ANDQ AX,SI
43 ANDQ AX,DX
47 ANDQ AX,CX
51 ANDQ AX,R8
55 ANDQ AX,R9
63 CMPQ AX,DX
65 CMPQ AX,CX
67 CMPQ AX,R8
[all …]
/external/llvm/test/CodeGen/X86/
Dpromote-vec3.ll23 ; SSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
37 ; SSE41-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
51 ; AVX_ANY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
65 ; AVX_X86_64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
89 ; SSE3-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
104 ; SSE41-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
119 ; AVX_ANY-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
134 ; AVX_X86_64-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
Danyext.ll11 ; X32-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
20 ; X64-NEXT: # kill: %EAX<def> %EAX<kill> %AX<def>
38 ; X32-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
47 ; X64-NEXT: # kill: %AX<def> %AX<kill> %EAX<def>
Dextractelement-index.ll136 ; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
142 ; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
152 ; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
158 ; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
168 ; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
174 ; AVX-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
185 ; SSE-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
192 ; AVX1-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
200 ; AVX2-NEXT: # kill: %AX<def> %AX<kill> %EAX<kill>
Dcrash-O0.ll9 ; aliased registers (AX and AL) - RegAllocFast does not like that.
34 ; CQO defines implicitly AX and DIV64 uses it implicitly too.
36 ; AX for the vreg defined in between and the compiler crashed.
Dpr21792.ll36 ; CHECK-NEXT: movd %xmm0, %r[[AX:..]]
37 ; CHECK-NEXT: movslq %e[[AX]],
38 ; CHECK-NEXT: sarq $32, %r[[AX]]
Dpeephole-na-phys-copy-folding.ll149 ; CHECK32-NEXT: movl %[[AX:eax]], %[[TMP:e[ds]i]]
153 ; CHECK64-NEXT: mov{{[lq]}} %[[AX:[er]ax]], %[[TMP:rdx]]
157 ; CHECK-NEXT: push{{[lq]}} %[[AX]]
159 ; CHECK-NEXT: mov{{[lq]}} %[[TMP]], %[[AX]]
163 ; CHECK-NEXT: pop{{[lq]}} %[[AX]]
/external/elfutils/tests/
Drun-readelf-z.sh30 [ 1] .text PROGBITS 0000000000400078 00000078 0000002a 0 AX 0 0 1
52 [ 1] .text PROGBITS 0000000010000078 00000078 00000074 0 AX 0 0 8
75 [ 1] .text PROGBITS 0000000000400078 00000078 0000002a 0 AX 0 0 1
97 [ 1] .text PROGBITS 0000000010000078 00000078 00000074 0 AX 0 0 8
120 [ 1] .text PROGBITS 08048054 000054 00002a 0 AX 0 0 1
142 [ 1] .text PROGBITS 01800054 000054 000074 0 AX 0 0 1
165 [ 1] .text PROGBITS 08048054 000054 00002a 0 AX 0 0 1
187 [ 1] .text PROGBITS 01800054 000054 000074 0 AX 0 0 1
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/X86/
Dintel-syntax.txt36 # CHECK: add AX, 0
48 # CHECK: adc AX, 0
60 # CHECK: cmp AX, 0
72 # CHECK: test AX, 0
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td46 // AL is really implied by AX, but the registers in Defs must match the
48 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
56 let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
59 []>, OpSize; // AX,DX = AX*GR16
70 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
80 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
83 []>, OpSize; // AX,DX = AX*[mem16]
95 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
98 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
100 OpSize; // AX,DX = AX*GR16
[all …]
DX86InstrExtension.td15 let Defs = [AX], Uses = [AL] in
17 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
18 let Defs = [EAX], Uses = [AX] in
20 "{cwtl|cwde}", []>; // EAX = signext(AX)
22 let Defs = [AX,DX], Uses = [AX] in
24 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
/external/clang/test/Layout/
Dms-x86-primary-bases.cpp167 struct AX : B0X, B1X { int a; AX() : a(0xf000000A) {} virtual void f() { printf("A"); } }; in f() function
324 sizeof(AX)+
Dms-x86-aligned-tail-padding.cpp352 struct AX : B0X, virtual B2X, virtual B6X, virtual B3X { struct
354 AX() : a(0xf000000A) {} in AX() function
531 sizeof(AX)+
Dms-x86-lazy-empty-nonvirtual-base.cpp623 struct AX : B1X, B2X, B3X, B4X, virtual B0X { struct
625 AX() : a(0x0000000A) { printf(" A = %p\n", this); } in AX() function
831 sizeof(AX)+
/external/syslinux/gpxe/src/doc/
Dpxe_extensions9 returned in AX. The status field in the parameter
49 returned in AX. The status field in the parameter
82 returned in AX. The status field in the parameter
121 returned in AX. The status field in the parameter
171 returned in AX. The status field in the parameter
207 returned in AX. The Status field in the parameter
242 returned in AX. The Status field in the parameter
247 proper value on entry, AX will contain PXENV_EXIT_SUCCESS,
292 returned in AX. The Status field in the parameter
/external/boringssl/src/ssl/test/runner/poly1305/
Dpoly1305_amd64.s33 MOVL 8(CX),AX
43 ANDL $0X0FFFFFFC,AX
47 MOVL AX,120(SP)
464 MOVQ 104(SP),AX
465 ANDQ R9,AX
466 ORQ AX,SI
468 MOVQ 112(SP),AX
469 ANDQ R9,AX
470 ORQ AX,DX
472 MOVQ 120(SP),AX
[all …]
/external/llvm/test/MC/X86/
Dintel-syntax.s417 div AX, BX
425 idiv AX, BX
457 xchg AX, CX
458 xchg CX, AX
470 xchg AX, [ECX]
471 xchg [ECX], AX
485 test AX, [ECX]
486 test [ECX], AX
496 fnstsw AX
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td57 // AL is really implied by AX, but the registers in Defs must match the
60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
67 // AX,DX = AX*GR16
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
93 // AX,DX = AX*[mem16]
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
115 // AX,DX = AX*GR16
116 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
[all …]
DX86InstrExtension.td15 let Defs = [AX], Uses = [AL] in
17 "{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
18 let Defs = [EAX], Uses = [AX] in
20 "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
22 let Defs = [AX,DX], Uses = [AX] in
24 "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
/external/libpcap/msdos/
Dpkt_rx1.s71 ; 1st time (AX=0) it requests an address where to put the packet
73 ; 2nd time (AX=1) the packet has been copied to this location (DS:SI)
93 cmp ax, 0 ; first call? (AX=0)
94 jne @post ; AX=1: second call, do post process
Dpkt_rx0.asm115 ; 1st time (AX=0) it requests an address where to put the packet
117 ; 2nd time (AX=1) the packet has been copied to this location (DS:SI)
142 cmp ax, 0 ; first call? (AX=0)
143 jne @post ; AX=1: second call, do post process
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dinline-asm.ll4 ; Dest is AX, dest type = i32.
10 ; input is AX, in type = i32.

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