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Searched refs:BITCAST (Results 1 – 25 of 71) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
64 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
65 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
71 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
72 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
91 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
92 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
DLegalizeVectorOps.cpp255 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in PromoteVectorOp()
262 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in PromoteVectorOp()
287 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); in ExpandVSELECT()
288 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); in ExpandVSELECT()
DLegalizeVectorTypes.cpp51 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
140 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in ScalarizeVecRes_BITCAST()
313 case ISD::BITCAST: in ScalarizeVectorOperand()
347 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), in ScalarizeVecOp_BITCAST()
423 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; in SplitVectorResult()
542 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
543 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
551 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
552 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
566 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
[all …]
DSelectionDAGBuilder.cpp130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); in getCopyFromParts()
163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); in getCopyFromParts()
164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); in getCopyFromParts()
206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromParts()
284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in getCopyFromPartsVector()
364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in getCopyToParts()
407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, in getCopyToParts()
425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); in getCopyToParts()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypesGeneric.cpp63 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
64 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
76 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
84 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
89 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
90 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
100 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
101 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
[all …]
DLegalizeVectorOps.cpp418 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); in Promote()
429 return DAG.getNode(ISD::BITCAST, dl, VT, Op); in Promote()
754 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); in ExpandSELECT()
755 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); in ExpandSELECT()
764 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); in ExpandSELECT()
808 ISD::BITCAST, DL, VT, in ExpandANY_EXTEND_VECTOR_INREG()
859 return DAG.getNode(ISD::BITCAST, DL, VT, in ExpandZERO_EXTEND_VECTOR_INREG()
883 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0)); in ExpandBSWAP()
885 return DAG.getNode(ISD::BITCAST, DL, VT, Op); in ExpandBSWAP()
911 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0)); in ExpandBITREVERSE()
[all …]
DLegalizeDAG.cpp489 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value); in LegalizeStoreOps()
658 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res); in LegalizeLoadOps()
1375 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value); in getSignAsIntValue()
1423 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue); in modifySignAsInt()
2351 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); in ExpandLegalINT_TO_FP()
2352 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr); in ExpandLegalINT_TO_FP()
2885 case ISD::BITCAST: in ExpandNode()
2969 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), in ExpandNode()
3021 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); in ExpandNode()
3022 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); in ExpandNode()
[all …]
DLegalizeVectorTypes.cpp52 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
168 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecRes_BITCAST()
433 case ISD::BITCAST: in ScalarizeVectorOperand()
483 return DAG.getNode(ISD::BITCAST, SDLoc(N), in ScalarizeVecOp_BITCAST()
594 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; in SplitVectorResult()
767 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
768 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
776 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
777 Hi = DAG.getNode(ISD::BITCAST, dl, HiVT, Hi); in SplitVecRes_BITCAST()
791 Lo = DAG.getNode(ISD::BITCAST, dl, LoVT, Lo); in SplitVecRes_BITCAST()
[all …]
/external/llvm/test/CodeGen/X86/
Dvshift-6.ll12 ; B = BITCAST MVT::v16i8, A
16 ; D = BITCAST MVT::v16i8, C
/external/llvm/test/Transforms/PGOProfile/
Dicp_vararg.ll16 ; ICALL-PROM: [[BITCAST:%[0-9]+]] = bitcast i32 (i32, ...)* %tmp to i8*
17 ; ICALL-PROM: [[CMP:%[0-9]+]] = icmp eq i8* [[BITCAST]], bitcast (i32 (i32, ...)* @va_func to i8*)
Dindirect_call_promotion.ll38 ; ICALL-PROM: [[BITCAST:%[0-9]+]] = bitcast i32 ()* %tmp to i8*
39 ; ICALL-PROM: [[CMP:%[0-9]+]] = icmp eq i8* [[BITCAST]], bitcast (i32 ()* @func4 to i8*)
Dicp_covariant_call_return.ll25 ; ICALL-PROM: [[BITCAST:%[0-9]+]] = bitcast %struct.Base* (%struct.B*)* %tmp3 to i8*
26 ; ICALL-PROM: [[CMP:%[0-9]+]] = icmp eq i8* [[BITCAST]], bitcast (%struct.Derived* (%struct.D*)* @…
Dicp_covariant_invoke_return.ll35 ; ICALL-PROM: [[BITCAST:%[0-9]+]] = bitcast %struct.Base* (%struct.B*)* %tmp3 to i8*
36 ; ICALL-PROM: [[CMP:%[0-9]+]] = icmp eq i8* [[BITCAST]], bitcast (%struct.Derived* (%struct.D*)* @…
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp351 setOperationAction(ISD::BITCAST, MVT::i32, Legal); in SPUTargetLowering()
352 setOperationAction(ISD::BITCAST, MVT::f32, Legal); in SPUTargetLowering()
353 setOperationAction(ISD::BITCAST, MVT::i64, Legal); in SPUTargetLowering()
354 setOperationAction(ISD::BITCAST, MVT::f64, Legal); in SPUTargetLowering()
678 DAG.getNode(ISD::BITCAST, dl, vecVT, result)); in LowerLOAD()
691 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones); in LowerLOAD()
717 result = DAG.getNode(ISD::BITCAST, dl, vecVT, in LowerLOAD()
890 DAG.getNode(ISD::BITCAST, dl, in LowerSTORE()
919 ones = DAG.getNode(ISD::BITCAST, dl, MVT::i128, ones); in LowerSTORE()
933 Value = DAG.getNode(ISD::BITCAST, dl, MVT::i128, Value); in LowerSTORE()
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp474 setTargetDAGCombine(ISD::BITCAST); in AMDGPUTargetLowering()
1031 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in split64BitValue()
1045 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getLoHalf64()
1053 SDValue Vec = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Op); in getHiHalf64()
1365 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV)); in LowerUDIVREM64()
1366 Results.push_back(DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM)); in LowerUDIVREM64()
1376 REM = DAG.getNode(ISD::BITCAST, DL, MVT::i64, REM); in LowerUDIVREM64()
1407 DIV = DAG.getNode(ISD::BITCAST, DL, MVT::i64, DIV); in LowerUDIVREM64()
1652 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src); in LowerFTRUNC()
1668 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64); in LowerFTRUNC()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp670 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
1162 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1292 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
1805 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
1875 } else if (Use->getOpcode() == ISD::BITCAST) { in isUsedByReturnOnly()
2564 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3030 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); in LowerFP_TO_INT()
3080 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); in LowerINT_TO_FP()
3091 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
3103 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); in X86TargetLowering()
333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); in X86TargetLowering()
335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); in X86TargetLowering()
337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); in X86TargetLowering()
784 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); in X86TargetLowering()
785 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); in X86TargetLowering()
786 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); in X86TargetLowering()
787 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); in X86TargetLowering()
1140 setTargetDAGCombine(ISD::BITCAST); in X86TargetLowering()
1460 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); in LowerReturn()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcISelLowering.cpp208 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); in LowerFormalArguments()
216 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments()
263 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); in LowerFormalArguments()
430 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
520 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); in LowerCall()
728 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in SparcTargetLowering()
729 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in SparcTargetLowering()
929 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); in LowerFP_TO_SINT()
935 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); in LowerSINT_TO_FP()
1049 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V), in LowerVAARG()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp901 setOperationAction(ISD::BITCAST, MVT::i64, Custom); in ARMTargetLowering()
1518 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); in LowerCallResult()
1666 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerCall()
2296 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); in LowerReturn()
2424 } else if (Copy->getOpcode() == ISD::BITCAST) { in isUsedByReturnOnly()
3323 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); in LowerFormalArguments()
3407 } else if (Op->getOpcode() == ISD::BITCAST && in isFloatingPointZero()
4249 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || in LowerFCOPYSIGN()
4261 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), in LowerFCOPYSIGN()
4269 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), in LowerFCOPYSIGN()
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.cpp542 if (N->getOpcode() == ISD::BITCAST) in selectVSplatCommon()
618 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmPow2()
649 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskL()
683 if (N->getOpcode() == ISD::BITCAST) in selectVSplatMaskR()
705 if (N->getOpcode() == ISD::BITCAST) in selectVSplatUimmInvPow2()
/external/llvm/lib/Target/SystemZ/
DSystemZISelLowering.cpp291 setOperationAction(ISD::BITCAST, VT, Legal); in SystemZTargetLowering()
427 setOperationAction(ISD::BITCAST, MVT::i32, Custom); in SystemZTargetLowering()
428 setOperationAction(ISD::BITCAST, MVT::f32, Custom); in SystemZTargetLowering()
829 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
852 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value); in convertValVTToLocVT()
2350 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask); in lowerVectorSETCC()
2779 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64); in lowerBITCAST()
2787 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64); in lowerBITCAST()
3095 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op); in lowerCTPOP()
3101 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op); in lowerCTPOP()
[all …]
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-bitcast.ll3 ; Used to fail with "Cannot BITCAST between types of different sizes!"
Dvect-bitcast-1.ll3 …`VT.getSizeInBits() == Operand.getValueType().getSizeInBits() && "Cannot BITCAST between types of …
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCISelLowering.cpp183 setOperationAction(ISD::BITCAST, MVT::f32, Expand); in PPCTargetLowering()
184 setOperationAction(ISD::BITCAST, MVT::i32, Expand); in PPCTargetLowering()
185 setOperationAction(ISD::BITCAST, MVT::i64, Expand); in PPCTargetLowering()
186 setOperationAction(ISD::BITCAST, MVT::f64, Expand); in PPCTargetLowering()
3688 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0)); in LowerSINT_TO_FP()
3909 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res); in BuildSplatI()
3938 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS); in BuildVSLDOI()
3939 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS); in BuildVSLDOI()
3945 return DAG.getNode(ISD::BITCAST, dl, VT, T); in BuildVSLDOI()
3979 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z); in LowerBUILD_VECTOR()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h425 BITCAST, enumerator

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