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Searched refs:BUILD_VECTOR (Results 1 – 25 of 65) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Darm64-build-vector.ll48 ; fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
49 ; -> (BUILD_VECTOR A, B, ..., C, D, ...)
Darm64-ext.ll95 ; chosen to reach lowering phase as a BUILD_VECTOR.
Daarch64-smull.ll235 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
269 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
Darm64-dup.ll295 ; We used to spot this as a BUILD_VECTOR implementable by dup, but assume that
298 ; BUILD_VECTOR will have an i32 as its source). In that case, the operation is
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp429 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in SPUTargetLowering()
1098 SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T); in LowerConstantFP()
1677 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T)); in LowerBUILD_VECTOR()
1687 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T)); in LowerBUILD_VECTOR()
1697 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size())); in LowerBUILD_VECTOR()
1705 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); in LowerBUILD_VECTOR()
1709 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T); in LowerBUILD_VECTOR()
1731 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in LowerV2I64Splat()
1747 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, in LowerV2I64Splat()
1760 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in LowerV2I64Splat()
[all …]
DSPUISelDAGToDAG.cpp124 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getCarryGenerateShufMask()
139 return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in getBorrowGenerateShufMask()
665 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in Select()
673 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in Select()
681 shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in Select()
823 signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl, in Select()
837 SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, in Select()
1188 } else if (i64vec.getOpcode() == ISD::BUILD_VECTOR) { in SelectI64Constant()
DSPUOperands.td34 assert(N->getOpcode() == ISD::BUILD_VECTOR
35 && "LO16_vec got something other than a BUILD_VECTOR");
60 assert(N->getOpcode() == ISD::BUILD_VECTOR
61 && "HI16_vec got something other than a BUILD_VECTOR");
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp52 case ISD::BUILD_VECTOR: R = N->getOperand(0); break; in ScalarizeVectorResult()
357 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), N->getValueType(0), in ScalarizeVecOp_CONCAT_VECTORS()
424 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, &LoOps[0], LoOps.size()); in SplitVecRes_BUILD_VECTOR()
580 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, &HiOps[0], HiOps.size()); in SplitVecRes_BUILD_VECTOR()
930 Output = DAG.getNode(ISD::BUILD_VECTOR,dl,NewVT, &SVOps[0], SVOps.size()); in SplitVecRes_VECTOR_SHUFFLE()
1165 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), in SplitVecOp_CONCAT_VECTORS()
1233 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; in WidenVectorResult()
1533 return DAG.getNode(ISD::BUILD_VECTOR, DL, WidenVT, &Ops[0], WidenNumElts); in WidenVecRes_Convert()
1657 NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, in WidenVecRes_BITCAST()
[all …]
DLegalizeTypesGeneric.cpp289 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, Parts, 2); in ExpandOp_BITCAST()
323 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandOp_BUILD_VECTOR()
384 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElts); in ExpandOp_SCALAR_TO_VECTOR()
DSelectionDAG.cpp116 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllOnes()
157 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllZeros()
196 if (N->getOpcode() != ISD::BUILD_VECTOR) in isScalarToVector()
768 case ISD::BUILD_VECTOR: { in VerifyNodeCommon()
974 Result = getNode(ISD::BUILD_VECTOR, DebugLoc(), VT, &Ops[0], Ops.size()); in getConstant()
1017 Result = getNode(ISD::BUILD_VECTOR, DebugLoc(), VT, &Ops[0], Ops.size()); in getConstantFP()
2692 if (N1.getOpcode() == ISD::BUILD_VECTOR && in getNode()
2693 N2.getOpcode() == ISD::BUILD_VECTOR) { in getNode()
2697 return getNode(ISD::BUILD_VECTOR, DL, VT, &Elts[0], Elts.size()); in getNode()
2870 if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { in getNode()
[all …]
DDAGCombiner.cpp1107 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); in visit()
1550 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { in tryFoldToZero()
1554 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, in tryFoldToZero()
4350 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4368 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, in visitZERO_EXTEND()
4952 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && in visitBITCAST()
5132 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5189 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
5226 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, in ConstantFoldBITCASTofBUILD_VECTOR()
6784 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) in visitINSERT_VECTOR_ELT()
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DLegalizeVectorOps.cpp368 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); in UnrollVSETCC()
/external/llvm/test/CodeGen/X86/
Dvbinop-simplify-bug.ll12 ; Cannot select: 0x2e329d0: v4i32 = BUILD_VECTOR 0x2e2ea00, 0x2e2ea00, 0x2e2ea00, 0x2e2ea00
D2011-12-28-vselecti8.ll7 ; wider BUILD_VECTOR. This causes the introduction of a new
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp53 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
497 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Op); in ScalarizeVecOp_UnaryOp()
505 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), N->getValueType(0), Ops); in ScalarizeVecOp_CONCAT_VECTORS()
595 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
802 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, LoVT, LoOps); in SplitVecRes_BUILD_VECTOR()
805 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, HiVT, HiOps); in SplitVecRes_BUILD_VECTOR()
1412 Output = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, SVOps); in SplitVecRes_VECTOR_SHUFFLE()
1655 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, ElementOps); in SplitVecOp_EXTRACT_VECTOR_ELT()
1923 return DAG.getNode(ISD::BUILD_VECTOR, DL, N->getValueType(0), Elts); in SplitVecOp_CONCAT_VECTORS()
2059 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break; in WidenVectorResult()
[all …]
DLegalizeTypesGeneric.cpp371 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, in ExpandOp_BITCAST()
405 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandOp_BUILD_VECTOR()
467 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in ExpandOp_SCALAR_TO_VECTOR()
DLegalizeVectorOps.cpp623 Value = DAG.getNode(ISD::BUILD_VECTOR, dl, in ExpandLoad()
733 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand) in ExpandSELECT()
749 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops); in ExpandSELECT()
1066 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in UnrollVSETCC()
/external/llvm/test/CodeGen/ARM/
Dvector-DAGCombine.ll72 ; Test folding a binary vector operation with constant BUILD_VECTOR
136 ; a BUILD_VECTOR with i32 0 operands, which did not match the i16 operands
137 ; of the other BUILD_VECTOR.
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h253 BUILD_VECTOR, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h269 BUILD_VECTOR, enumerator
/external/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp1840 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in CompactSwizzlableVector()
1882 assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); in ReorganizeVector()
1921 assert(BuildVector.getOpcode() == ISD::BUILD_VECTOR); in OptimizeSwizzle()
2009 if (!isOperationLegal(ISD::BUILD_VECTOR, VT)) in PerformDAGCombine()
2021 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2051 if (Arg.getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2058 Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { in PerformDAGCombine()
2117 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
2136 if (Arg.getOpcode() != ISD::BUILD_VECTOR) in PerformDAGCombine()
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvector-DAGCombine.ll64 ; Test folding a binary vector operation with constant BUILD_VECTOR
Dvext.ll78 ; chosen to reach lowering phase as a BUILD_VECTOR.
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); in addTypeForNEON()
515 setTargetDAGCombine(ISD::BUILD_VECTOR); in ARMTargetLowering()
915 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; in getTargetNodeName()
4001 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); in LowerBUILD_VECTOR()
4035 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); in LowerBUILD_VECTOR()
4319 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, in LowerVECTOR_SHUFFLEv8i8()
4323 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, in LowerVECTOR_SHUFFLEv8i8()
4440 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); in LowerVECTOR_SHUFFLE()
4499 BVN->getOpcode() != ISD::BUILD_VECTOR) in isExtendedBUILD_VECTOR()
4520 if (N->getOpcode() != ISD::BUILD_VECTOR) in isExtendedBUILD_VECTOR()
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp165 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in InitAMDILLowering()
220 setOperationAction(ISD::BUILD_VECTOR, MVT::Other, Custom); in InitAMDILLowering()

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