| /external/swiftshader/third_party/LLVM/include/llvm/ADT/ |
| D | BitVector.h | 26 class BitVector {
38 friend class BitVector; variable
46 reference(BitVector &b, unsigned Idx) { in reference()
73 BitVector() : Size(0), Capacity(0) { in BitVector() function
79 explicit BitVector(unsigned s, bool t = false) : Size(s) { in Size()
88 BitVector(const BitVector &RHS) : Size(RHS.size()) { in BitVector() function
100 ~BitVector() { in ~BitVector()
224 BitVector &set() { in set()
230 BitVector &set(unsigned Idx) { in set()
235 BitVector &reset() { in reset()
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| D | SmallBitVector.h | 87 BitVector *getPointer() const { in getPointer()
89 return reinterpret_cast<BitVector *>(X); in getPointer()
98 void switchToLarge(BitVector *BV) { in switchToLarge()
144 switchToLarge(new BitVector(s, t));
152 switchToLarge(new BitVector(*RHS.getPointer())); in SmallBitVector()
254 BitVector *BV = new BitVector(N, t);
267 BitVector *BV = new BitVector(SmallSize); in reserve()
413 switchToLarge(new BitVector(*RHS.getPointer()));
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| D | PackedVector.h | 30 static T getValue(const llvm::BitVector &Bits, unsigned Idx) { in getValue()
37 static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { in setValue()
47 static T getValue(const llvm::BitVector &Bits, unsigned Idx) { in getValue()
56 static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { in setValue()
77 llvm::BitVector Bits;
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| /external/llvm/include/llvm/ADT/ |
| D | BitVector.h | 27 class BitVector {
43 friend class BitVector; variable
51 reference(BitVector &b, unsigned Idx) { in reference()
78 BitVector() : Size(0), Capacity(0) { in BitVector() function
84 explicit BitVector(unsigned s, bool t = false) : Size(s) { in Size()
93 BitVector(const BitVector &RHS) : Size(RHS.size()) { in BitVector() function
105 BitVector(BitVector &&RHS) in BitVector() function
111 ~BitVector() { in ~BitVector()
219 BitVector &set() { in set()
225 BitVector &set(unsigned Idx) { in set()
[all …]
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| D | SmallBitVector.h | 91 BitVector *getPointer() const { in getPointer()
93 return reinterpret_cast<BitVector *>(X); in getPointer()
102 void switchToLarge(BitVector *BV) { in switchToLarge()
148 switchToLarge(new BitVector(s, t));
156 switchToLarge(new BitVector(*RHS.getPointer())); in SmallBitVector()
249 BitVector *BV = new BitVector(N, t);
262 BitVector *BV = new BitVector(SmallSize); in reserve()
488 switchToLarge(new BitVector(*RHS.getPointer()));
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| /external/v8/src/ |
| D | bit-vector.h | 14 class BitVector : public ZoneObject {
19 explicit Iterator(BitVector* target) in Iterator()
53 BitVector* target_;
58 friend class BitVector; variable
65 BitVector(int length, Zone* zone) in BitVector() function
73 BitVector(const BitVector& other, Zone* zone) in BitVector() function
85 void CopyFrom(const BitVector& other) { in CopyFrom()
113 void Union(const BitVector& other) { in Union()
120 bool UnionIsChanged(const BitVector& other) { in UnionIsChanged()
131 void Intersect(const BitVector& other) { in Intersect()
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| D | bit-vector.cc | 13 void BitVector::Print() { in Print()
28 void BitVector::Iterator::Advance() { in Advance()
43 int BitVector::Count() const { in Count()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 60 BitVector CalleeSavedRegs;
64 BitVector ReservedRegs;
69 BitVector RegsAvailable;
99 void getRegsUsed(BitVector &used, bool includeReserved);
103 BitVector getRegsAvailable(const TargetRegisterClass *RC);
141 void setUsed(BitVector &Regs) { in setUsed()
144 void setUnused(BitVector &Regs) { in setUnused()
149 void addRegWithSubRegs(BitVector &BV, unsigned Reg);
152 void addRegWithAliases(BitVector &BV, unsigned Reg);
160 BitVector &Candidates,
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| /external/v8/src/crankshaft/ |
| D | hydrogen-environment-liveness.h | 30 void ZapEnvironmentSlotsInSuccessors(HBasicBlock* block, BitVector* live);
32 void UpdateLivenessAtBlockEnd(HBasicBlock* block, BitVector* live);
33 void UpdateLivenessAtInstruction(HInstruction* instr, BitVector* live);
45 ZoneList<BitVector*> live_at_block_start_;
47 ZoneList<BitVector*> first_simulate_invalid_for_index_;
59 BitVector went_live_since_last_simulate_;
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| D | hydrogen-infer-representation.cc | 24 ZoneList<BitVector*> connected_phis(phi_count, zone()); in Run()
27 BitVector* connected_set = new(zone()) BitVector(phi_count, zone()); in Run()
57 BitVector done(phi_count, zone()); in Run()
64 for (BitVector::Iterator it(connected_phis[i]); in Run()
77 for (BitVector::Iterator it(connected_phis[i]); in Run()
86 for (BitVector::Iterator it(connected_phis[i]); in Run()
106 for (BitVector::Iterator it(connected_phis[i]); in Run()
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| D | hydrogen-environment-liveness.cc | 28 new(zone()) BitVector(maximum_environment_size_, zone()), zone()); in HEnvironmentLivenessAnalysisPhase()
31 new(zone()) BitVector(maximum_environment_size_, zone()), zone()); in HEnvironmentLivenessAnalysisPhase()
48 HBasicBlock* block, BitVector* live) { in ZapEnvironmentSlotsInSuccessors()
54 BitVector* live_in_successor = live_at_block_start_[successor_id]; in ZapEnvironmentSlotsInSuccessors()
85 BitVector* live) { in UpdateLivenessAtBlockEnd()
96 BitVector* live) { in UpdateLivenessAtInstruction()
165 BitVector live(maximum_environment_size_, zone()); in Run()
166 BitVector worklist(block_count_, zone()); in Run()
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| D | lithium-allocator.h | 23 class BitVector; variable
376 BitVector* assigned_registers() { in assigned_registers()
379 BitVector* assigned_double_registers() { in assigned_double_registers()
398 BitVector* ComputeLiveOut(HBasicBlock* block);
399 void AddInitialIntervals(HBasicBlock* block, BitVector* live_out);
400 void ProcessInstructions(HBasicBlock* block, BitVector* live);
519 ZoneList<BitVector*> live_in_sets_;
542 BitVector* assigned_registers_;
543 BitVector* assigned_double_registers_;
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 64 BitVector RegUnitsAvailable;
68 BitVector KillRegUnits, DefRegUnits;
69 BitVector TmpRegUnits;
110 BitVector getRegsAvailable(const TargetRegisterClass *RC);
157 void setUsed(BitVector &RegUnits) { in setUsed()
160 void setUnused(BitVector &RegUnits) { in setUnused()
169 void addRegUnits(BitVector &BV, unsigned Reg);
176 BitVector &Candidates,
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| /external/llvm/lib/CodeGen/ |
| D | SafeStackColoring.h | 37 BitVector Begin;
39 BitVector End;
41 BitVector LiveIn;
43 BitVector LiveOut;
50 BitVector bv;
82 BitVector InterestingAllocas;
125 static inline raw_ostream &operator<<(raw_ostream &OS, const BitVector &V) {
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| D | SpillPlacement.h | 38 class BitVector; variable
54 BitVector *ActiveNodes;
108 void prepare(BitVector &RegBundles);
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| D | StackColoring.cpp | 257 BitVector Begin;
259 BitVector End;
261 BitVector LiveIn;
263 BitVector LiveOut;
290 BitVector InterestingSlots;
294 BitVector ConservativeSlots;
312 void dumpBV(const char *tag, const BitVector &BV) const;
368 typedef DenseMap<const MachineBasicBlock*, BitVector> BlockBitVecMap;
391 const BitVector &BV) const { in dumpBV()
507 BitVector BetweenStartEnd; in collectMarkers()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RegisterScavenging.cpp | 74 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB); in initRegState()
111 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { in addRegWithSubRegs()
117 void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) { in addRegWithAliases()
151 BitVector EarlyClobberRegs(NumPhysRegs); in forward()
152 BitVector KillRegs(NumPhysRegs); in forward()
153 BitVector DefRegs(NumPhysRegs); in forward()
154 BitVector DeadRegs(NumPhysRegs); in forward()
231 void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) { in getRegsUsed()
251 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { in getRegsAvailable()
252 BitVector Mask(TRI->getNumRegs()); in getRegsAvailable()
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| D | SpillPlacement.h | 36 class BitVector; variable
50 BitVector *ActiveNodes;
97 void prepare(BitVector &RegBundles);
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenMux.cpp | 67 BitVector Defs, Uses;
69 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
89 void getSubRegs(unsigned Reg, BitVector &SRs) const;
90 void expandReg(unsigned Reg, BitVector &Set) const;
91 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
92 BitVector &Uses) const;
108 void HexagonGenMux::getSubRegs(unsigned Reg, BitVector &SRs) const { in getSubRegs()
114 void HexagonGenMux::expandReg(unsigned Reg, BitVector &Set) const { in expandReg()
122 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses()
123 BitVector &Uses) const { in getDefsUses()
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| /external/swiftshader/third_party/LLVM/unittests/ADT/ |
| D | BitVectorTest.cpp | 21 BitVector Vec; in TEST()
45 BitVector Inv = ~Vec; in TEST()
79 BitVector Copy = Vec; in TEST()
80 BitVector Alt(3, false); in TEST()
134 Inv = ~BitVector(); in TEST()
152 BitVector A; in TEST()
157 BitVector B; in TEST()
191 BitVector Vec(3); in TEST()
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| /external/v8/src/compiler/ |
| D | liveness-analyzer.h | 23 void ClearNonLiveFrameStateSlots(Node* frame_state, BitVector* liveness);
40 Node* ClearNonLiveStateValues(Node* frame_state, BitVector* liveness);
52 BitVector permanently_live_;
140 void Process(BitVector* result, NonLiveFrameStateSlotReplacer* relaxer);
141 bool UpdateLive(BitVector* working_area);
159 BitVector live_;
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| D | frame.h | 87 void SetAllocatedRegisters(BitVector* regs) { in SetAllocatedRegisters()
92 void SetAllocatedDoubleRegisters(BitVector* regs) { in SetAllocatedDoubleRegisters()
156 BitVector* allocated_registers_;
157 BitVector* allocated_double_registers_;
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| D | ast-loop-assignment-analyzer.h | 24 BitVector* GetVariablesAssignedInLoop(IterationStatement* loop) { in GetVariablesAssignedInLoop()
38 ZoneVector<std::pair<IterationStatement*, BitVector*>> list_;
59 ZoneDeque<BitVector*> loop_stack_;
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.h | 30 BitVector SGPRPressureSets;
31 BitVector VGPRPressureSets;
33 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
35 BitVector &PressureSets) const;
49 BitVector getReservedRegs(const MachineFunction &MF) const override;
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| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 75 const TargetRegisterClass *RC, BitVector &R){ in getAllocatableSetForRC()
81 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, in getAllocatableSet()
83 BitVector Allocatable(getNumRegs()); in getAllocatableSet()
94 BitVector Reserved = getReservedRegs(MF); in getAllocatableSet()
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