| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 109 Bitcast, enumerator
375 return Flags & (1 << MCID::Bitcast); in isBitcast()
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 109 Bitcast, enumerator
274 bool isBitcast() const { return Flags & (1 << MCID::Bitcast); } in isBitcast()
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| /external/clang/test/Coverage/ |
| D | codegen-next.m | 6 // Bitcast requires types of same width
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| /external/llvm/lib/Transforms/Vectorize/ |
| D | LoadStoreVectorizer.cpp | 806 Value *Bitcast = in vectorizeStoreChain() local
808 StoreInst *SI = cast<StoreInst>(Builder.CreateStore(Vec, Bitcast)); in vectorizeStoreChain()
928 Value *Bitcast = in vectorizeLoadChain() local
931 LoadInst *LI = cast<LoadInst>(Builder.CreateLoad(Bitcast)); in vectorizeLoadChain()
938 InstrsToReorder.push_back(cast<Instruction>(Bitcast)); in vectorizeLoadChain()
965 InstrsToReorder.push_back(cast<Instruction>(Bitcast)); in vectorizeLoadChain()
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| /external/llvm/test/Assembler/ |
| D | ConstantExprFoldCast.ll | 27 ; Bitcast -> GEP
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| /external/llvm/test/CodeGen/SPARC/ |
| D | float-constants.ll | 6 ;; Bitcast should not do a runtime conversion, but rather emit a
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| /external/spirv-llvm/test/SPIRV/transcoding/ |
| D | OpPhi_ArgumentsPlaceholders.ll | 50 ;CHECK-SPIRV: Bitcast {{[0-9]+}} [[BitcastResultId]] [[LoadResultId]]
|
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| D | SPIRVOpCodeEnum.h | 115 _SPIRV_OP(Bitcast, 124)
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| D | SPIRVInstruction.h | 1094 _SPIRV_OP(Bitcast)
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 510 return hasProperty(MCID::Bitcast, Type);
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| /external/spirv-llvm/lib/SPIRV/ |
| D | SPIRVInternal.h | 102 _SPIRV_OP(BitCast, Bitcast) in init()
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| /external/clang/include/clang/Basic/ |
| D | BuiltinsNVPTX.def | 386 // Bitcast
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfoV5.td | 685 // Bitcast is different than [fp|sint|uint]_to_[sint|uint|fp].
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenInstrInfo.inc | 5434 …{ 1250, 2, 1, 0, 0, "MMX_MOVD64from64rr", 0|(1<<MCID::Bitcast), 0xfc002103ULL, NULL, NULL, Operand…
5439 …{ 1255, 2, 1, 0, 0, "MMX_MOVD64rrv164", 0|(1<<MCID::Bitcast), 0xdc002105ULL, NULL, NULL, OperandIn…
5659 …{ 1475, 2, 1, 0, 0, "MOV64toSDrr", 0|(1<<MCID::Bitcast), 0xdd002145ULL, NULL, NULL, OperandInfo102…
5691 …{ 1507, 2, 1, 0, 0, "MOVDI2SSrr", 0|(1<<MCID::Bitcast), 0xdd000145ULL, NULL, NULL, OperandInfo105 …
5737 …{ 1553, 2, 1, 0, 0, "MOVSDto64rr", 0|(1<<MCID::Bitcast), 0xfd002143ULL, NULL, NULL, OperandInfo109…
5744 …{ 1560, 2, 1, 0, 0, "MOVSS2DIrr", 0|(1<<MCID::Bitcast), 0xfd000143ULL, NULL, NULL, OperandInfo108 …
7312 …{ 3128, 2, 1, 0, 0, "VMOV64toSDrr", 0|(1<<MCID::Bitcast), 0x6dd000145ULL, NULL, NULL, OperandInfo1…
7336 …{ 3152, 2, 1, 0, 0, "VMOVDI2SSrr", 0|(1<<MCID::Bitcast), 0x2dd000145ULL, NULL, NULL, OperandInfo10…
7400 …{ 3216, 2, 1, 0, 0, "VMOVSDto64rr", 0|(1<<MCID::Bitcast), 0x4fd000143ULL, NULL, NULL, OperandInfo1…
7410 …{ 3226, 2, 1, 0, 0, "VMOVSS2DIrr", 0|(1<<MCID::Bitcast), 0x2fd000143ULL, NULL, NULL, OperandInfo10…
|
| D | X86InstrSSE.td | 4165 // Bitcast FR64 <-> GR64
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 10706 SDNode *Bitcast = *Trunc->use_begin(); in PerformDAGCombine() local
10709 if (Bitcast->getOpcode() != ISD::BITCAST || in PerformDAGCombine()
10710 Bitcast->getValueType(0) != MVT::f32) in PerformDAGCombine()
10717 std::swap(Bitcast, Bitcast2); in PerformDAGCombine()
10751 DCI.CombineTo(Bitcast, FloatLoad2); in PerformDAGCombine()
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| /external/swiftshader/third_party/LLVM/test/Transforms/ObjCARC/ |
| D | basic.ll | 683 ; Bitcast insertion
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 1008 // Bitcast i32 -> f32. NEON prefers to use VMOVDRR.
|
| D | ARMISelLowering.cpp | 4765 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0)); in lowerCTPOP32BitElements() local
4766 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG); in lowerCTPOP32BitElements()
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| /external/llvm/test/Transforms/ObjCARC/ |
| D | basic.ll | 1287 ; Bitcast insertion
|
| /external/llvm/include/llvm/IR/ |
| D | IntrinsicsNVVM.td | 707 // Bitcast
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 851 // Bitcast
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrSSE.td | 4781 // Bitcast FR64 <-> GR64
|