Home
last modified time | relevance | path

Searched refs:CONCAT_VECTORS (Results 1 – 25 of 34) sorted by relevance

12

/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp316 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
425 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
598 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, &LoOps[0], LoOps.size()); in SplitVecRes_CONCAT_VECTORS()
601 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, &HiOps[0], HiOps.size()); in SplitVecRes_CONCAT_VECTORS()
975 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; in SplitVectorOperand()
1028 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1184 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); in SplitVecOp_VSETCC()
1203 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in SplitVecOp_FP_ROUND()
1234 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break; in WidenVectorResult()
1435 ConcatOps[SubConcatIdx] = DAG.getNode(ISD::CONCAT_VECTORS, dl, in WidenVecRes_Binary()
[all …]
DLegalizeIntegerTypes.cpp89 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
600 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
762 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
DSelectionDAG.cpp2480 case ISD::CONCAT_VECTORS: in getNode()
2689 case ISD::CONCAT_VECTORS: in getNode()
2858 N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
3114 case ISD::CONCAT_VECTORS: in getNode()
6010 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
DSelectionDAGBuilder.cpp260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, in getCopyFromPartsVector()
2819 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), in visitShuffleVector()
2835 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
2838 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp446 case ISD::CONCAT_VECTORS: in ScalarizeVectorOperand()
596 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
823 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); in SplitVecRes_CONCAT_VECTORS()
826 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); in SplitVecRes_CONCAT_VECTORS()
1463 case ISD::CONCAT_VECTORS: Res = SplitVecOp_CONCAT_VECTORS(N); break; in SplitVectorOperand()
1557 return DAG.getNode(ISD::CONCAT_VECTORS, DL, Src0VT, LoSelect, HiSelect); in SplitVecOp_VSELECT()
1574 return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi); in SplitVecOp_UnaryOp()
1733 SDValue Res = DAG.getNode(ISD::CONCAT_VECTORS, dl, MGT->getValueType(0), Lo, in SplitVecOp_MGATHER()
1977 SDValue InterVec = DAG.getNode(ISD::CONCAT_VECTORS, DL, InterVT, HalfLo, in SplitVecOp_TruncateHelper()
2005 SDValue Con = DAG.getNode(ISD::CONCAT_VECTORS, DL, WideResVT, LoRes, HiRes); in SplitVecOp_VSETCC()
[all …]
DDAGCombiner.cpp1433 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); in visit()
5280 assert(LHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
5281 RHS.getOpcode() == ISD::CONCAT_VECTORS && in ConvertSelectToConcatVector()
5321 ISD::CONCAT_VECTORS, dl, VT, in ConvertSelectToConcatVector()
5532 SDValue GatherRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); in visitMGATHER()
5616 SDValue LoadRes = DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); in visitMLOAD()
5689 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi); in visitVSELECT()
5702 if (N1.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
5703 N2.getOpcode() == ISD::CONCAT_VECTORS && in visitVSELECT()
6000 SDValue NewValue = DAG.getNode(ISD::CONCAT_VECTORS, DL, DstVT, Loads); in CombineExtLoad()
[all …]
DSelectionDAGDumper.cpp220 case ISD::CONCAT_VECTORS: return "concat_vectors"; in getOperationName()
DSelectionDAG.cpp3052 case ISD::CONCAT_VECTORS: in getNode()
3489 case ISD::CONCAT_VECTORS: { in getNode()
3688 N1.getOpcode() == ISD::CONCAT_VECTORS && in getNode()
3954 case ISD::CONCAT_VECTORS: { in getNode()
5494 case ISD::CONCAT_VECTORS: { in getNode()
DLegalizeIntegerTypes.cpp102 case ISD::CONCAT_VECTORS: in PromoteIntegerResult()
724 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); in PromoteIntRes_TRUNCATE()
888 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break; in PromoteIntegerOperand()
DLegalizeDAG.cpp2981 case ISD::CONCAT_VECTORS: { in ExpandNode()
4266 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps); in PromoteNode()
4389 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts); in PromoteNode()
DSelectionDAGBuilder.cpp320 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
3056 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurSDLoc(), in visitShuffleVector()
3070 : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
3073 : DAG.getNode(ISD::CONCAT_VECTORS, in visitShuffleVector()
/external/llvm/test/CodeGen/X86/
Dwiden_shuffle-1.ll68 ; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
81 ; PR11389: another CONCAT_VECTORS case
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h270 CONCAT_VECTORS, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h286 CONCAT_VECTORS, enumerator
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dwiden_shuffle-1.ll50 ; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1956 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE in HexagonTargetLowering()
1983 setOperationAction(ISD::CONCAT_VECTORS, NativeVT, Custom); in HexagonTargetLowering()
1999 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i8, Custom); in HexagonTargetLowering()
2000 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i16, Custom); in HexagonTargetLowering()
2001 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i32, Custom); in HexagonTargetLowering()
2002 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i64, Custom); in HexagonTargetLowering()
2004 setOperationAction(ISD::CONCAT_VECTORS, MVT::v256i8, Custom); in HexagonTargetLowering()
2005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v128i16, Custom); in HexagonTargetLowering()
2006 setOperationAction(ISD::CONCAT_VECTORS, MVT::v64i32, Custom); in HexagonTargetLowering()
2007 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i64, Custom); in HexagonTargetLowering()
[all …]
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp265 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in AMDGPUTargetLowering()
266 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); in AMDGPUTargetLowering()
267 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in AMDGPUTargetLowering()
268 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in AMDGPUTargetLowering()
707 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
1106 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad), in SplitVectorLoad()
/external/llvm/test/CodeGen/ARM/
Dvector-DAGCombine.ll31 ; Check CONCAT_VECTORS DAG combiner pass doesn't introduce illegal types.
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp844 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); in X86TargetLowering()
845 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); in X86TargetLowering()
846 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); in X86TargetLowering()
847 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); in X86TargetLowering()
848 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); in X86TargetLowering()
1004 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); in X86TargetLowering()
1005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); in X86TargetLowering()
1006 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); in X86TargetLowering()
1007 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); in X86TargetLowering()
1008 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); in X86TargetLowering()
[all …]
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h376 X86_INTRINSIC_DATA(avx512_kunpck_bw, KUNPCK, ISD::CONCAT_VECTORS, 0),
377 X86_INTRINSIC_DATA(avx512_kunpck_dq, KUNPCK, ISD::CONCAT_VECTORS, 0),
378 X86_INTRINSIC_DATA(avx512_kunpck_wd, KUNPCK, ISD::CONCAT_VECTORS, 0),
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp483 setTargetDAGCombine(ISD::CONCAT_VECTORS); in AArch64TargetLowering()
676 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
5020 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
5396 return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, V0, V1); in tryFormConcatFromShuffle()
5534 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V1Cst); in GenerateTBL()
5542 V1Cst = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v16i8, V1Cst, V2Cst); in GenerateTBL()
5618 } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) { in LowerVECTOR_SHUFFLE()
8118 DAG.getNode(ISD::CONCAT_VECTORS, dl, ConcatTy, in performConcatVectorsCombine()
8682 return DAG.getNode(ISD::CONCAT_VECTORS, DL, ResVT, Lo, Hi); in performExtendCombine()
9876 case ISD::CONCAT_VECTORS: in PerformDAGCombine()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.cpp120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); in addTypeForNEON()
4787 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
4822 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
4977 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
7108 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
7109 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
7126 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, in PerformVECTOR_SHUFFLECombine()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp116 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); in addTypeForNEON()
5952 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec, in ReconstructShuffle()
6310 if (V1->getOpcode() == ISD::CONCAT_VECTORS && V2->isUndef()) { in LowerVECTOR_SHUFFLE()
6328 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0), in LowerVECTOR_SHUFFLE()
6806 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerSDIV()
6842 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); in LowerUDIV()
7195 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); in LowerOperation()
9853 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
9854 Op1.getOpcode() != ISD::CONCAT_VECTORS || in PerformVECTOR_SHUFFLECombine()
9870 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, in PerformVECTOR_SHUFFLECombine()
/external/llvm/lib/CodeGen/
DTargetLoweringBase.cpp867 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); in initActions()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td554 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",

12