| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.cpp | 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
98 Ops[4].getAsInteger(10, CRm); in parseGenericRegister()
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
110 uint32_t CRm = (Bits >> 3) & 0xf; in genericRegisterString() local
114 utostr(CRm) + "_" + utostr(Op2); in genericRegisterString()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 311 // Op0 Op1 CRn CRm Op2
366 // Op0 Op1 CRn CRm Op2
405 // Op0 Op1 CRn CRm Op2
416 // Op0 Op1 CRn CRm Op2
421 // Op0 Op1 CRn CRm Op2
431 // Op0 Op1 CRn CRm Op2
437 // Op0 Op1 CRn CRm Op2
442 // Op0 Op1 CRn CRm Op2
454 // Op0 Op1 CRn CRm Op2
709 // Op0 Op1 CRn CRm Op2
[all …]
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| D | AArch64InstrFormats.td | 856 // Hint instructions that take both a CRm and a 3-bit immediate.
870 // CRm. op2 differentiates the opcodes.
881 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
883 bits<4> CRm;
885 let Inst{11-8} = CRm;
896 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
923 // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
|
| D | AArch64InstrInfo.td | 405 [(int_aarch64_dmb (i32 imm32_0_15:$CRm))]>;
408 [(int_aarch64_dsb (i32 imm32_0_15:$CRm))]>;
411 [(int_aarch64_isb (i32 imm32_0_15:$CRm))]>;
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4161 bits<4> CRm;
4168 let Inst{3-0} = CRm;
4174 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4183 bits<4> CRm;
4189 let Inst{3-0} = CRm;
4196 c_imm:$CRm, imm0_7:$opc2),
4198 imm:$CRm, imm:$opc2)]>,
4200 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4202 c_imm:$CRm, 0, pred:$p)>;
[all …]
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| D | ARMInstrInfo.td | 4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4816 imm:$CRm, imm:$opc2)]>,
4823 bits<4> CRm;
4825 let Inst{3-0} = CRm;
4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4838 imm:$CRm, imm:$opc2)]>,
4846 bits<4> CRm;
4848 let Inst{3-0} = CRm;
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 4215 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4218 imm:$CRm, imm:$opc2)]> {
4224 bits<4> CRm;
4226 let Inst{3-0} = CRm;
4236 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4239 imm:$CRm, imm:$opc2)]> {
4246 bits<4> CRm;
4248 let Inst{3-0} = CRm;
[all …]
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| D | ARMInstrThumb2.td | 3620 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3630 bits<4> CRm;
3637 let Inst{3-0} = CRm;
3644 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3645 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3654 bits<4> CRm;
3660 let Inst{3-0} = CRm;
3667 c_imm:$CRm, imm0_7:$opc2),
3669 imm:$CRm, imm:$opc2)]>;
3672 c_imm:$CRm, imm0_7:$opc2),
[all …]
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 202 V_(CRm, 11, 8, Bits)
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| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 139 V_(CRm, 11, 8, ExtractBits) \
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| D | assembler-aarch64.cc | 1416 Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(xt)); in sys()
2061 void Assembler::clrex(int imm4) { Emit(CLREX | CRm(imm4)); } in clrex()
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| D | assembler-aarch64.h | 2816 static Instr CRm(int imm4) { in CRm() function
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| /external/clang/lib/CodeGen/ |
| D | CGBuiltin.cpp | 4038 Value *CRm = EmitScalarExpr(E->getArg(3)); in EmitARMBuiltinExpr() local
4045 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm}); in EmitARMBuiltinExpr()
4064 Value *CRm = EmitScalarExpr(E->getArg(2)); in EmitARMBuiltinExpr() local
4065 Value *RtAndRt2 = Builder.CreateCall(F, {Coproc, Opc1, CRm}); in EmitARMBuiltinExpr()
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 5273 unsigned CRm = fieldFromInstruction(Val, 0, 4); in DecoderForMRRC2AndMCRR2() local
5309 Inst.addOperand(MCOperand::createImm(CRm)); in DecoderForMRRC2AndMCRR2()
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| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 6829 UInt CRm = INSN(11,8); in dis_ARM64_branch_etc() local
6830 vassert(opc <= 2 && CRm <= 15); in dis_ARM64_branch_etc()
6837 DIP("%s %s\n", opNames[opc], howNames[CRm]); in dis_ARM64_branch_etc()
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