| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.cpp | 93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0; in parseGenericRegister() local
97 Ops[3].getAsInteger(10, CRn); in parseGenericRegister()
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2; in parseGenericRegister()
109 uint32_t CRn = (Bits >> 7) & 0xf; in genericRegisterString() local
113 return "S" + utostr(Op0) + "_" + utostr(Op1) + "_C" + utostr(CRn) + "_C" + in genericRegisterString()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SystemOperands.td | 311 // Op0 Op1 CRn CRm Op2
366 // Op0 Op1 CRn CRm Op2
405 // Op0 Op1 CRn CRm Op2
416 // Op0 Op1 CRn CRm Op2
421 // Op0 Op1 CRn CRm Op2
431 // Op0 Op1 CRn CRm Op2
437 // Op0 Op1 CRn CRm Op2
442 // Op0 Op1 CRn CRm Op2
454 // Op0 Op1 CRn CRm Op2
709 // Op0 Op1 CRn CRm Op2
[all …]
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| D | AArch64InstrFormats.td | 896 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4162 bits<4> CRn;
4169 let Inst{19-16} = CRn;
4195 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4197 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4200 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4201 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4204 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4206 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4210 def : t2InstAlias<"mcr2${p} $cop, $opc1, $Rt, $CRn, $CRm",
[all …]
|
| D | ARMInstrInfo.td | 4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4815 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4819 bits<4> CRn;
4830 let Inst{19-16} = CRn;
4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4837 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4842 bits<4> CRn;
4853 let Inst{19-16} = CRn;
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3620 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3631 bits<4> CRn;
3638 let Inst{19-16} = CRn;
3666 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3668 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3671 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3673 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3678 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3682 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
3685 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
[all …]
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| D | ARMInstrInfo.td | 4215 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4217 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4220 bits<4> CRn;
4231 let Inst{19-16} = CRn;
4236 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4238 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4242 bits<4> CRn;
4253 let Inst{19-16} = CRn;
[all …]
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| /external/v8/src/arm64/ |
| D | constants-arm64.h | 201 V_(CRn, 15, 12, Bits) \
|
| /external/vixl/src/aarch64/ |
| D | constants-aarch64.h | 138 V_(CRn, 15, 12, ExtractBits) \
|
| D | assembler-aarch64.h | 2821 static Instr CRn(int imm4) { in CRn() function
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| D | assembler-aarch64.cc | 1416 Emit(SYS | ImmSysOp1(op1) | CRn(crn) | CRm(crm) | ImmSysOp2(op2) | Rt(xt)); in sys()
|