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Searched refs:CTLZ (Results 1 – 25 of 58) sorted by relevance

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/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll8 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTLZ]]
48 ; SI-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTLZ]]
128 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
129 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTLZ]]
147 ; ALL-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
148 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTLZ]]
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll9 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
10 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTLZ]]
28 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %A, i1 true)
29 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTLZ]]
48 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %A, i1 true)
49 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTLZ]]
177 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true)
178 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTLZ]] to i64
200 ; ALL: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true)
201 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTLZ]] to i32
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dctlz.ll21 ; SI-DAG: s_flbit_i32_b32 [[CTLZ:s[0-9]+]], [[VAL]]
23 ; SI-DAG: v_mov_b32_e32 [[VCTLZ:v[0-9]+]], [[CTLZ]]
38 ; SI-DAG: v_ffbh_u32_e32 [[CTLZ:v[0-9]+]], [[VAL]]
39 ; SI-DAG: v_cmp_eq_i32_e32 vcc, 0, [[CTLZ]]
40 ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], [[CTLZ]], 32, vcc
102 ; SI-DAG: v_cmp_eq_i32_e32 vcc, 0, [[CTLZ]]
121 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
123 ; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
145 ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[ADD]], [[CMPHI]]
148 ; SI-DAG: v_cndmask_b32_e64 v[[CLTZ_LO:[0-9]+]], v[[CTLZ:[0-9]+]], 64, vcc
Dctlz_zero_undef.ll101 ; SI-DAG: v_cndmask_b32_e32 v[[CTLZ:[0-9]+]], [[VFFBH_HI]], [[VFFBH_LO]]
103 ; SI: {{buffer|flat}}_store_dwordx2 v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
124 ; SI-DAG: v_cndmask_b32_e64 v[[CTLZ:[0-9]+]], [[FFBH_HI]], [[FFBH_LO]]
126 ; SI: {{buffer|flat}}_store_dwordx2 {{.*}}v{{\[}}[[CTLZ]]:[[CTLZ_HI]]{{\]}}
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll8 ; CHECK-NEXT: [[CTLZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %A, i1 true)
9 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
28 ; CHECK-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTLZ]]
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dnon-vectorizable-intrinsic.ll6 ; CTLZ cannot be vectorized currently because the second argument is a scalar
9 ; Test causes an assert if LLVM tries to vectorize CTLZ.
/external/llvm/lib/Transforms/Utils/
DIntegerDivision.cpp183 Function *CTLZ = Intrinsic::getDeclaration(F->getParent(), Intrinsic::ctlz, in generateUnsignedDivisionCode() local
255 Value *Tmp0 = Builder.CreateCall(CTLZ, {Divisor, True}); in generateUnsignedDivisionCode()
256 Value *Tmp1 = Builder.CreateCall(CTLZ, {Dividend, True}); in generateUnsignedDivisionCode()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h320 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h342 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp74 setOperationAction(ISD::CTLZ, MVT::i16, Promote); in BlackfinTargetLowering()
113 setOperationAction(ISD::CTLZ, MVT::i32, Expand); in BlackfinTargetLowering()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp160 case ISD::CTLZ: in LegalizeOp()
DLegalizeIntegerTypes.cpp60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
315 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); in PromoteIntRes_CTLZ()
1101 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break; in ExpandIntegerResult()
1705 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo); in ExpandIntRes_CTLZ()
1706 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi); in ExpandIntRes_CTLZ()
DLegalizeVectorTypes.cpp68 case ISD::CTLZ: in ScalarizeVectorResult()
444 case ISD::CTLZ: in SplitVectorResult()
982 case ISD::CTLZ: in SplitVectorOperand()
1295 case ISD::CTLZ: in WidenVectorResult()
DLegalizeDAG.cpp2834 case ISD::CTLZ: { in ExpandBitCount()
2867 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) in ExpandBitCount()
2870 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); in ExpandBitCount()
2968 case ISD::CTLZ: in ExpandNode()
3838 case ISD::CTLZ: in PromoteNode()
3851 } else if (Node->getOpcode() == ISD::CTLZ) { in PromoteNode()
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp113 setOperationAction(ISD::CTLZ, MVT::i32, Promote); in SystemZTargetLowering()
114 setOperationAction(ISD::CTLZ, MVT::i64, Legal); in SystemZTargetLowering()
/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h773 ISD::CTLZ, 0),
775 ISD::CTLZ, 0),
777 ISD::CTLZ, 0),
779 ISD::CTLZ, 0),
781 ISD::CTLZ, 0),
783 ISD::CTLZ, 0),
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeDAG.cpp2685 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); in ExpandBitCount()
2686 case ISD::CTLZ: { in ExpandBitCount()
2692 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op); in ExpandBitCount() local
2696 DAG.getConstant(len, dl, VT), CTLZ); in ExpandBitCount()
2732 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) in ExpandBitCount()
2735 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); in ExpandBitCount()
2748 case ISD::CTLZ: in ExpandNode()
4012 case ISD::CTLZ: in PromoteNode()
4029 if (Node->getOpcode() == ISD::CTLZ || in PromoteNode()
DLegalizeVectorOps.cpp286 case ISD::CTLZ: in LegalizeOp()
1032 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ; in ExpandCTLZ_CTTZ_ZERO_UNDEF()
DSelectionDAGDumper.cpp321 case ISD::CTLZ: return "ctlz"; in getOperationName()
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp127 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
128 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp300 setOperationAction(ISD::CTLZ , MVT::i8, Promote); in SPUTargetLowering()
301 setOperationAction(ISD::CTLZ , MVT::i16, Promote); in SPUTargetLowering()
302 setOperationAction(ISD::CTLZ , MVT::i32, Legal); in SPUTargetLowering()
303 setOperationAction(ISD::CTLZ , MVT::i64, Expand); in SPUTargetLowering()
304 setOperationAction(ISD::CTLZ , MVT::i128, Expand); in SPUTargetLowering()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp120 setOperationAction(ISD::CTLZ, MVT::i8, Expand); in MSP430TargetLowering()
121 setOperationAction(ISD::CTLZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp102 setOperationAction(ISD::CTLZ, MVT::i64, Custom); in BPFTargetLowering()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUISelLowering.cpp309 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
345 setOperationAction(ISD::CTLZ, MVT::i64, Custom); in AMDGPUTargetLowering()
398 setOperationAction(ISD::CTLZ, VT, Expand); in AMDGPUTargetLowering()
723 case ISD::CTLZ: in LowerOperation()
2474 return Opc == ISD::CTLZ || Opc == ISD::CTLZ_ZERO_UNDEF; in isCtlzOpc()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp158 setOperationAction(ISD::CTLZ, VT, Expand); in InitAMDILLowering()

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