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Searched refs:CTTZ (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/test/Transforms/SimplifyCFG/AMDGPU/
Dcttz-ctlz.ll68 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 64, i64 [[CTTZ]]
88 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 32, i32 [[CTTZ]]
108 ; SI-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; SI-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i16 16, i16 [[CTTZ]]
187 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
188 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i64 63, i64 [[CTTZ]]
207 ; ALL-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
208 ; ALL-NEXT: [[SEL:%[A-Za-z0-9.]+]] = select i1 [[ICMP]], i32 31, i32 [[CTTZ]]
[all …]
/external/llvm/test/Transforms/SimplifyCFG/X86/
Dspeculate-cttz-ctlz.ll68 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
69 ; ALL-NEXT: select i1 [[COND]], i64 64, i64 [[CTTZ]]
88 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %A, i1 true)
89 ; ALL-NEXT: select i1 [[COND]], i32 32, i32 [[CTTZ]]
108 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %A, i1 true)
109 ; ALL-NEXT: select i1 [[COND]], i16 16, i16 [[CTTZ]]
131 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 true)
132 ; ALL: [[ZEXT:%[A-Za-z0-9]+]] = zext i32 [[CTTZ]] to i64
154 ; ALL: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 true)
155 ; ALL: [[TRUNC:%[A-Za-z0-9]+]] = trunc i64 [[CTTZ]] to i32
[all …]
/external/llvm/test/Transforms/InstCombine/
Dffs-1.ll108 ; CHECK-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
109 ; CHECK-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
119 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i32 @llvm.cttz.i32(i32 %x, i1 true)
120 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i32 [[CTTZ]], 1
130 ; CHECK-FFS-NEXT: [[CTTZ:%[a-z0-9]+]] = call i64 @llvm.cttz.i64(i64 %x, i1 true)
131 ; CHECK-FFS-NEXT: [[INC:%[a-z0-9]+]] = add nuw nsw i64 [[CTTZ]], 1
/external/llvm/test/Transforms/SimplifyCFG/PowerPC/
Dcttz-ctlz-spec.ll27 ; CHECK-NEXT: [[CTTZ:%[A-Za-z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DISDOpcodes.h320 BSWAP, CTTZ, CTLZ, CTPOP, enumerator
/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h342 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE, enumerator
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelLowering.cpp75 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in BlackfinTargetLowering()
114 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in BlackfinTargetLowering()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp159 case ISD::CTTZ: in LegalizeOp()
DLegalizeIntegerTypes.cpp62 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break; in PromoteIntegerResult()
339 return DAG.getNode(ISD::CTTZ, dl, NVT, Op); in PromoteIntRes_CTTZ()
1103 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break; in ExpandIntegerResult()
1735 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo); in ExpandIntRes_CTTZ()
1736 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi); in ExpandIntRes_CTTZ()
DLegalizeVectorTypes.cpp70 case ISD::CTTZ: in ScalarizeVectorResult()
446 case ISD::CTTZ: in SplitVectorResult()
981 case ISD::CTTZ: in SplitVectorOperand()
1297 case ISD::CTTZ: in WidenVectorResult()
DLegalizeDAG.cpp2855 case ISD::CTTZ: { in ExpandBitCount()
2969 case ISD::CTTZ: in ExpandNode()
3837 case ISD::CTTZ: in PromoteNode()
3844 if (Node->getOpcode() == ISD::CTTZ) { in PromoteNode()
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZISelLowering.cpp111 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in SystemZTargetLowering()
112 setOperationAction(ISD::CTTZ, MVT::i64, Expand); in SystemZTargetLowering()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp287 case ISD::CTTZ: in LegalizeOp()
1032 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ; in ExpandCTLZ_CTTZ_ZERO_UNDEF()
DSelectionDAGDumper.cpp319 case ISD::CTTZ: return "cttz"; in getOperationName()
DLegalizeDAG.cpp2719 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op); in ExpandBitCount()
2720 case ISD::CTTZ: { in ExpandBitCount()
2750 case ISD::CTTZ: in ExpandNode()
4010 case ISD::CTTZ: in PromoteNode()
4017 if (Node->getOpcode() == ISD::CTTZ) { in PromoteNode()
DLegalizeVectorTypes.cpp75 case ISD::CTTZ: in ScalarizeVectorResult()
631 case ISD::CTTZ: in SplitVectorResult()
1498 case ISD::CTTZ: in SplitVectorOperand()
2152 case ISD::CTTZ: in WidenVectorResult()
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430ISelLowering.cpp125 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
126 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DSPUISelLowering.cpp294 setOperationAction(ISD::CTTZ , MVT::i8, Expand); in SPUTargetLowering()
295 setOperationAction(ISD::CTTZ , MVT::i16, Expand); in SPUTargetLowering()
296 setOperationAction(ISD::CTTZ , MVT::i32, Expand); in SPUTargetLowering()
297 setOperationAction(ISD::CTTZ , MVT::i64, Expand); in SPUTargetLowering()
298 setOperationAction(ISD::CTTZ , MVT::i128, Expand); in SPUTargetLowering()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp118 setOperationAction(ISD::CTTZ, MVT::i8, Expand); in MSP430TargetLowering()
119 setOperationAction(ISD::CTTZ, MVT::i16, Expand); in MSP430TargetLowering()
/external/llvm/lib/Target/BPF/
DBPFISelLowering.cpp101 setOperationAction(ISD::CTTZ, MVT::i64, Custom); in BPFTargetLowering()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDILISelLowering.cpp157 setOperationAction(ISD::CTTZ, VT, Expand); in InitAMDILLowering()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelLowering.cpp170 setOperationAction(ISD::CTTZ, MVT::i32, Expand); in MBlazeTargetLowering()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1861 setOperationAction(ISD::CTTZ, MVT::i8, Promote); in HexagonTargetLowering()
1862 setOperationAction(ISD::CTTZ, MVT::i16, Promote); in HexagonTargetLowering()
1942 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, in HexagonTargetLowering()
/external/swiftshader/third_party/LLVM/lib/Target/Alpha/
DAlphaISelLowering.cpp90 setOperationAction(ISD::CTTZ , MVT::i64 , Expand); in AlphaTargetLowering()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp589 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom); in ARMTargetLowering()
590 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom); in ARMTargetLowering()
591 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom); in ARMTargetLowering()
592 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in ARMTargetLowering()
594 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom); in ARMTargetLowering()
595 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom); in ARMTargetLowering()
596 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom); in ARMTargetLowering()
597 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom); in ARMTargetLowering()
759 setOperationAction(ISD::CTTZ, MVT::i32, Custom); in ARMTargetLowering()
7185 case ISD::CTTZ: in LowerOperation()

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