| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 88 case ISD::CopyFromReg: NumberDeps++; break; in numberRCValPredInSU()
125 case ISD::CopyFromReg: break; in numberRCValSuccInSU()
456 case ISD::CopyFromReg: in SUSchedulingCost()
562 case ISD::CopyFromReg: in initNumRegDefsLeft()
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| D | StatepointLowering.cpp | 316 while (CallEnd->getOpcode() == ISD::CopyFromReg) in lowerCallFromStatepointLoweringInfo()
881 SDValue CopyFromReg = getCopyFromRegs(I, RetTy); in visitGCResult() local
883 assert(CopyFromReg.getNode()); in visitGCResult()
884 setValue(&CI, CopyFromReg); in visitGCResult()
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| D | ScheduleDAGRRList.cpp | 289 if (!Node->isMachineOpcode() && Node->getOpcode() == ISD::CopyFromReg) { in GetCostForDef()
682 case ISD::CopyFromReg: in EmitNode()
1192 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
2129 if (PN->getOpcode() == ISD::CopyFromReg) { in unscheduledNode()
2220 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2291 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2308 Pred.getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
2835 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
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| D | InstrEmitter.cpp | 354 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
850 if (F->getOpcode() == ISD::CopyFromReg) { in EmitMachineNode()
913 case ISD::CopyFromReg: { in EmitSpecialNode()
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| D | ScheduleDAGSDNodes.cpp | 122 if (Def->getOpcode() == ISD::CopyFromReg && in CheckForPhysRegDependency()
530 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
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| D | SelectionDAGDumper.cpp | 144 case ISD::CopyFromReg: return "CopyFromReg"; in getOperationName()
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| D | ScheduleDAGFast.cpp | 436 if (N->getOpcode() == ISD::CopyFromReg) { in getPhysicalRegisterVT()
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| D | LegalizeFloatTypes.cpp | 63 case ISD::CopyFromReg: in SoftenFloatResult()
799 case ISD::CopyFromReg: in CanSkipSoftenFloatOperand()
814 case ISD::CopyFromReg: in CanSkipSoftenFloatOperand()
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| D | SelectionDAGISel.cpp | 2250 UserOpcode == ISD::CopyFromReg || in WalkChainUsers()
2753 case ISD::CopyFromReg: in SelectCodeCommon()
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| /external/llvm/test/CodeGen/X86/ |
| D | merge-store-partially-alias-loads.ll | 18 ; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 165 CopyFromReg, enumerator
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| D | SelectionDAG.h | 425 return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
435 return getNode(ISD::CopyFromReg, dl, VTs, Ops, Glue.getNode() ? 3 : 2);
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| /external/llvm/lib/Target/X86/ |
| D | README-X86-64.txt | 46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
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| D | X86ISelDAGToDAG.cpp | 346 if (OtherOp->getOpcode() == ISD::CopyFromReg && in shouldAvoidImmediateInstFormsForSize()
1306 RHS.getNode()->getOpcode() == ISD::CopyFromReg || in matchAddressRecursively()
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | README-X86-64.txt | 46 emits a CopyFromReg which gets turned into a movb and that can be allocated a
49 To get around this, isel emits a CopyFromReg from AX and then right shift it
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 170 CopyFromReg, enumerator
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| D | SelectionDAG.h | 611 return getNode(ISD::CopyFromReg, dl, VTs, Ops);
621 return getNode(ISD::CopyFromReg, dl, VTs,
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 315 Op.getNode()->getOpcode() != ISD::CopyFromReg && in AddRegisterOperand()
710 if (F->getOpcode() == ISD::CopyFromReg) in EmitMachineNode()
820 case ISD::CopyFromReg: { in EmitSpecialNode()
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| D | ScheduleDAGRRList.cpp | 561 case ISD::CopyFromReg: in EmitNode()
2022 if (PN->getOpcode() == ISD::CopyFromReg) { in UnscheduledNode()
2116 PredSU->getNode()->getOpcode() == ISD::CopyFromReg) { in hasOnlyLiveInOpers()
2190 assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg && in resetVRegCycle()
2208 I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) { in hasVRegCycleUse()
2762 if (N->getOpcode() == ISD::CopyFromReg && in PrescheduleNodesWithMultipleUses()
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| D | ScheduleDAGSDNodes.cpp | 491 if (Node->getOpcode() == ISD::CopyFromReg) in InitNodeNumDefs()
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| D | SelectionDAGISel.cpp | 1629 User->getOpcode() == ISD::CopyFromReg || in WalkChainUsers()
2042 case ISD::CopyFromReg: in SelectCodeCommon()
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| D | SelectionDAGBuilder.cpp | 4368 if (CFR.getOpcode() == ISD::CopyFromReg) in getTruncatedArgReg()
4404 if (N.getOpcode() == ISD::CopyFromReg) in EmitFuncArgumentDbgValue()
6502 assert((Op.getOpcode() != ISD::CopyFromReg || in CopyValueToVirtualRegister()
6721 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { in LowerArguments()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUISelDAGToDAG.cpp | 512 ||Opc == ISD::CopyFromReg in DFormAddressPredicate()
533 if (Opc == ISD::CopyFromReg) { in DFormAddressPredicate()
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 294 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
300 N->getOpcode() != ISD::CopyFromReg;
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 294 // register. Truncate can be lowered to EXTRACT_SUBREG, and CopyFromReg may
300 N->getOpcode() != ISD::CopyFromReg;
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