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Searched refs:CreateReg (Results 1 – 25 of 81) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMAsmPrinter.cpp986 BrInst.addOperand(MCOperand::CreateReg(0)); in EmitJump2Table()
1031 Inst.addOperand(MCOperand::CreateReg(Dest)); in populateADROperands()
1035 Inst.addOperand(MCOperand::CreateReg(ccreg)); in populateADROperands()
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); in EmitInstruction()
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); in EmitInstruction()
1249 TmpInst.addOperand(MCOperand::CreateReg(0)); in EmitInstruction()
1251 TmpInst.addOperand(MCOperand::CreateReg(0)); in EmitInstruction()
1257 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); in EmitInstruction()
1267 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); in EmitInstruction()
1268 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); in EmitInstruction()
[all …]
DThumb2ITBlockPass.cpp188 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
213 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
DARMMCInstLower.cpp78 MCOp = MCOperand::CreateReg(MO.getReg()); in lowerOperand()
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86Disassembler.cpp161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
330 baseReg = MCOperand::CreateReg(X86::x); break; in translateRMMemory()
335 baseReg = MCOperand::CreateReg(0); in translateRMMemory()
345 indexReg = MCOperand::CreateReg(X86::x); break; in translateRMMemory()
351 indexReg = MCOperand::CreateReg(0); in translateRMMemory()
363 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6 in translateRMMemory()
365 baseReg = MCOperand::CreateReg(0); in translateRMMemory()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/
DMBlazeDisassembler.cpp538 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
539 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
540 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
546 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
547 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
548 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
558 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
565 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
571 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
580 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86MCInstLower.cpp315 MCOp = MCOperand::CreateReg(MO.getReg()); in Lower()
551 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest in LowerTlsAddr()
552 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base in LowerTlsAddr()
554 LEA.addOperand(MCOperand::CreateReg(0)); // index in LowerTlsAddr()
556 LEA.addOperand(MCOperand::CreateReg(0)); // seg in LowerTlsAddr()
559 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest in LowerTlsAddr()
560 LEA.addOperand(MCOperand::CreateReg(0)); // base in LowerTlsAddr()
562 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index in LowerTlsAddr()
564 LEA.addOperand(MCOperand::CreateReg(0)); // seg in LowerTlsAddr()
656 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg()); in EmitInstruction()
[all …]
DX86InstrBuilder.h65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, in getFullAddress()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
81 MO.push_back(MachineOperand::CreateReg(0, false, false, in getFullAddress()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h65 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, in getFullAddress()
73 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, in getFullAddress()
81 MO.push_back(MachineOperand::CreateReg(0, false, false, in getFullAddress()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp930 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
960 Inst.addOperand(MCOperand::CreateReg(getReg())); in addCCOutOperands()
965 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
971 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
972 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
980 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
996 Inst.addOperand(MCOperand::CreateReg(*I)); in addRegListOperands()
1154 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
1159 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
1178 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); in addAddrMode2Operands()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); in AddThumb1SBit()
642 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
644 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
652 MI.insert(I, MCOperand::CreateReg(0)); in AddThumbPredicate()
654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); in AddThumbPredicate()
857 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeGPRRegisterClass()
901 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodetcGPRRegisterClass()
928 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeSPRRegisterClass()
949 Inst.addOperand(MCOperand::CreateReg(Register)); in DecodeDPRRegisterClass()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/
DMBlazeAsmParser.cpp189 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
205 Inst.addOperand(MCOperand::CreateReg(getMemBase())); in addMemOperands()
209 Inst.addOperand(MCOperand::CreateReg(RegOff)); in addMemOperands()
230 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg() function
405 return MBlazeOperand::CreateReg(RegNo, S, E); in ParseRegister()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp205 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); in CreateVirtualRegisters()
220 MI->addOperand(MachineOperand::CreateReg(Reg, true)); in CreateVirtualRegisters()
232 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); in CreateVirtualRegisters()
328 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, in AddRegisterOperand()
353 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false)); in AddOperand()
514 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); in EmitSubregNode()
869 MI->addOperand(MachineOperand::CreateReg(Reg, true, in EmitSpecialNode()
877 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true, in EmitSpecialNode()
/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/
DX86AsmParser.cpp297 Inst.addOperand(MCOperand::CreateReg(getReg())); in addRegOperands()
307 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg())); in addMemOperands()
309 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg())); in addMemOperands()
311 Inst.addOperand(MCOperand::CreateReg(getMemSegReg())); in addMemOperands()
326 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) { in CreateReg() function
507 return X86Operand::CreateReg(RegNo, Start, End); in ParseOperand()
795 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); in ParseInstruction()
808 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); in ParseInstruction()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DLiveVariables.cpp244 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
256 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
268 LastDef->addOperand(MachineOperand::CreateReg(Reg, in HandlePhysRegUse()
382 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
606 Ret->addOperand(MachineOperand::CreateReg(*I, false, true)); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DLiveVariables.cpp247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
/external/llvm/lib/Target/PowerPC/
DPPCTOCRegDeps.cpp121 MI.addOperand(MachineOperand::CreateReg(PPC::X2, in processBlock()
/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp205 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
234 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
/external/mesa3d/src/gallium/drivers/radeon/
DAMDGPUMCInstLower.cpp51 MCOp = MCOperand::CreateReg(MO.getReg()); in lower()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp222 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
229 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430MCInstLower.cpp123 MCOp = MCOperand::CreateReg(MO.getReg()); in Lower()
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp596 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in addStackMapLiveVars()
644 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
758 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true)); in selectPatchpoint()
807 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
813 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/false)); in selectPatchpoint()
826 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
832 Ops.push_back(MachineOperand::CreateReg(Reg, /*IsDef=*/true, in selectPatchpoint()
1131 Op = MachineOperand::CreateReg(Reg, false); in selectIntrinsicCall()
1147 Op = MachineOperand::CreateReg(FuncInfo.InitializeRegForValue(Address), in selectIntrinsicCall()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsMCInstLower.cpp101 return MCOperand::CreateReg(MO.getReg()); in LowerOperand()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeMCInstLower.cpp129 MCOp = MCOperand::CreateReg(MO.getReg()); in Lower()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DFunctionLoweringInfo.h141 unsigned CreateReg(EVT VT);
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInst.h97 static MCOperand CreateReg(unsigned Reg) { in CreateReg() function

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