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Searched refs:DIL (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Transforms/Utils/
DAddDiscriminators.cpp189 const DILocation *DIL = I.getDebugLoc(); in addDiscriminators() local
190 if (!DIL) in addDiscriminators()
192 Location L = std::make_pair(DIL->getFilename(), DIL->getLine()); in addDiscriminators()
202 auto *Scope = DIL->getScope(); in addDiscriminators()
204 Builder.createFile(DIL->getFilename(), Scope->getDirectory()); in addDiscriminators()
207 I.setDebugLoc(DILocation::get(Ctx, DIL->getLine(), DIL->getColumn(), in addDiscriminators()
208 NewScope, DIL->getInlinedAt())); in addDiscriminators()
209 DEBUG(dbgs() << DIL->getFilename() << ":" << DIL->getLine() << ":" in addDiscriminators()
210 << DIL->getColumn() << ":" in addDiscriminators()
/external/llvm/lib/Transforms/IPO/
DSampleProfile.cpp468 const DILocation *DIL = DLoc; in getInstWeight() local
470 unsigned HeaderLineno = DIL->getScope()->getSubprogram()->getLine(); in getInstWeight()
473 uint32_t Discriminator = DIL->getDiscriminator(); in getInstWeight()
487 DEBUG(dbgs() << " " << Lineno << "." << DIL->getDiscriminator() << ":" in getInstWeight()
489 << DIL->getDiscriminator() << " - weight: " << R.get() in getInstWeight()
566 const DILocation *DIL = Inst.getDebugLoc(); in findCalleeFunctionSamples() local
567 if (!DIL) { in findCalleeFunctionSamples()
570 DISubprogram *SP = DIL->getScope()->getSubprogram(); in findCalleeFunctionSamples()
579 getOffset(DIL->getLine(), SP->getLine()), DIL->getDiscriminator())); in findCalleeFunctionSamples()
594 const DILocation *DIL = Inst.getDebugLoc(); in findFunctionSamples() local
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCTargetDesc.cpp108 X86::SIL, X86::DIL, X86::BPL, X86::SPL, X86::RAX, X86::RBX, in initLLVMToSEHAndCVRegMapping()
287 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
315 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
316 return X86::DIL; in getX86SubSuperRegisterOrZero()
352 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
388 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
424 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegisterOrZero()
DX86BaseInfo.h762 reg == X86::SIL || reg == X86::DIL); in isX86_64NonExtLowByteReg()
/external/llvm/test/CodeGen/X86/
Dipra-inline-asm.ll14 ; CHECK: foo Clobbered Registers: AH AL AX CH CL CX DI DIL EAX ECX EDI RAX RCX RDI
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.cpp425 Reserved.set(X86::DIL); in getReservedRegs()
691 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegister()
692 return X86::DIL; in getX86SubSuperRegister()
728 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegister()
764 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegister()
800 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: in getX86SubSuperRegister()
DX86RegisterInfo.td52 def DIL : Register<"dil">;
81 def DI : RegisterWithSubRegs<"di", [DIL]>;
279 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
285 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
289 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
DX86GenRegisterInfo.inc50 DIL = 31,
278 const unsigned DI_Overlaps[] = { X86::DI, X86::DIL, X86::EDI, X86::RDI, 0 };
279 const unsigned DIL_Overlaps[] = { X86::DIL, X86::DI, X86::EDI, X86::RDI, 0 };
295 const unsigned EDI_Overlaps[] = { X86::EDI, X86::DI, X86::DIL, X86::RDI, 0 };
357 const unsigned RDI_Overlaps[] = { X86::RDI, X86::DI, X86::DIL, X86::EDI, 0 };
413 const unsigned DI_SubRegsSet[] = { X86::DIL, 0 };
419 const unsigned EDI_SubRegsSet[] = { X86::DI, X86::DIL, 0 };
452 const unsigned RDI_SubRegsSet[] = { X86::EDI, X86::DI, X86::DIL, 0 };
596 { "DIL", DIL_Overlaps, Empty_SubRegsSet, DIL_SuperRegsSet },
730 …X86::AL, X86::CL, X86::DL, X86::AH, X86::CH, X86::DH, X86::BL, X86::BH, X86::SIL, X86::DIL, X86::B…
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DX86GenAsmWriter.inc6532 case X86::DIL:
DX86GenAsmWriter1.inc7275 case X86::DIL:
DX86GenAsmMatcher.inc2628 case X86::DIL: OpKind = MCK_GR8; break;
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td63 def DIL : X86Reg<"dil", 7>;
85 def DI : X86Reg<"di", 7, [DIL]>;
319 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
325 // instruction requiring a REX prefix, while SIL, DIL, BPL, R8D, etc.
329 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
DX86RegisterInfo.cpp485 Reserved.set(X86::DIL); in getReservedRegs()
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86BaseInfo.h542 reg == X86::SIL || reg == X86::DIL); in isX86_64NonExtLowByteReg()
DX86MCTargetDesc.cpp151 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH: in getX86RegNum()
/external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h86 ENTRY(DIL)
/external/llvm/lib/Target/X86/Disassembler/
DX86DisassemblerDecoder.h96 ENTRY(DIL)
/external/llvm/test/MC/X86/
Dintel-syntax.s29 mov BYTE PTR [RDX + RCX], DIL
/external/llvm/docs/TableGen/
Dindex.rst63 AH, AL, AX, BH, BL, BP, BPL, BX, CH, CL, CX, DH, DI, DIL, DL, DX, EAX, EBP, EBX,
/external/spirv-llvm/lib/SPIRV/
DSPIRVWriter.cpp138 DILocation* DIL = DL.get(); in transDbgInfo() local
139 auto File = BM->getString(DIL->getFilename().str()); in transDbgInfo()
/external/icu/icu4c/source/data/unidata/
DUnicodeData.txt14821 ABD7;MEETEI MAYEK LETTER DIL;Lo;0;L;;;;;N;;;;;
Dppucd.txt18049 cp;ABD7;na=MEETEI MAYEK LETTER DIL
/external/icu/icu4j/main/tests/core/src/com/ibm/icu/dev/data/unicode/
DUnicodeData.txt14821 ABD7;MEETEI MAYEK LETTER DIL;Lo;0;L;;;;;N;;;;;
/external/icu/android_icu4j/src/main/tests/android/icu/dev/data/unicode/
DUnicodeData.txt14821 ABD7;MEETEI MAYEK LETTER DIL;Lo;0;L;;;;;N;;;;;